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參數(shù)資料
| 型號： | PCM3001E |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM |
| 中文描述： | 立體聲音頻編解碼器18位，串行接口商標 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大小： | 212K |
| 代理商： | PCM3001E |
12
PCM3000/3001
FIGURE 4. Audio Data Input/Output Timing.
256f
S
, 384f
S
, or 512f
S
. When a 384f
S
or 512f
S
system clock
is used, the clock is divided into 256f
S
automatically. The
256f
S
clock is used to operate the digital filters and the
modulators.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, and Figures 5 and 6 illustrate
the typical system clock connections and external system
clock timing.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256f
S
8.1920
11.2896
12.2880
384f
S
12.2880
16.9340
18.4320
512f
S
16.3840
22.5792
24.5760
32
44.1
48
TABLE I. System Clock Frequencies.
t
BCH
t
BCY
t
BCL
t
LB
t
DIH
t
DIS
t
LRP
t
BL
t
LDO
t
BDO
BCKIN
LRCIN
DIN
DOUT
1.4V
1.4V
1.4V
0.5 x V
DD
BCKIN Pulse Cycle Time
t
BCY
t
BCH
t
BCL
t
BL
t
LB
t
LRP
t
DIS
t
DIH
t
BDO
t
LDO
t
RISE
t
FALL
300ns (min)
BCKIN Pulse Width High
120ns (min)
BCKIN Pulse Width Low
120ns (min)
BCKIN Rising Edge to LRCIN Edge
40ns (min)
LRCIN Edge to BCKIN Rising Edge
40ns (min)
LRCIN Pulse Width
t
BCY
(min)
40ns (min)
DIN Set-up Time
DIN Hold Time
40ns (min)
DOUT Delay Time to BCKIN Falling Edge
40ns (max)
DOUT Delay Time to LRCIN Edge
40ns (max)
Rising Time of All Signals
20ns (max)
Falling Time of All Signals
20ns (max)
SYSTEM CLOCK
The system clock for the PCM3000/3001 must be either 256f
S
,
384f
S
or 512f
S
, where f
S
is the audio sampling frequency. The
system clock can be either a crystal oscillator placed between
XTI (Pin 20) and XTO (Pin 21), or an external clock input. If
an external clock is used, the clock is provided to either XTI
or CLKIO (Pin 22), and XTO is open. The PCM3000/3001
has an XTI clock detection circuit which senses if an XTI
clock is operating. When the external clock is delivered to
XTI, CLKIO is a buffered output of XTI. When XTI is
connected to ground, the external clock must be tied to
CLKIO. For best performance, the “External Clock Input 2”
circuit in Figure 5 is recommended.
The PCM3000/3001 also has a system clock detection circuit
which automatically senses if the system clock is operating at
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