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參數(shù)資料
| 型號： | PCM1851PJT |
| 英文描述： | 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA |
| 中文描述： | 24位，96千赫立體聲A / D轉(zhuǎn)換器6 × 2通道的MUX和PGA |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 370K |
| 代理商： | PCM1851PJT |
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PCM1850
PCM1851
SLES108
MARCH 2004
www.ti.com
17
SERIAL AUDIO DATA INTERFACE
The PCM1850/1851 interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3).
Interface Mode
The PCM1850/1851 supports both master and slave modes as interface modes, and they are selected by mode control
via the serial port as shown in Table 4.
In master mode, the PCM1850/1851 provides the timing for serial audio data communications between the PCM1850/1851
and the digital audio processor or external circuit. While in slave mode, the PCM1850/1851 receives the timing for data
transfer from an external controller.
Table 4. Interface Mode
MD1
MD0
INTERFACE MODE
0
0
Slave mode (256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
) (default)
Master mode (256 f
S
)
Master mode (384 f
S
)
Master mode (512 f
S
)
0
1
1
0
1
1
Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the
clock and timing control circuit of the PCM1850/1851. The frequency of BCK is fixed at 64
×
LRCK. A 768-f
S
system clock
is not available in master mode.
Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1850/1851 accepts the 64 BCK/LRCK or 48 BCK/LRCK (only
for 384 f
S
SCKI) format. A 768-f
S
system clock is not available for f
S
= 88.2 kHz and 96 kHz in slave mode.
Data Format
The PCM1850/1851 supports four audio data formats in both master and slave modes, and they are selected by mode
control via the serial port as shown in Table 5. Figure 23 illustrates the data formats in both slave and master modes.
Table 5. Data Format
FORMAT NO.
FMT2
FMT1
FMT0
FORMAT
0
1
0
1
Left-justified, 24-bit
I
2
S, 24-bit, (default)
1
1
0
0
2
0
0
0
Right-justified, 24-bit
3
0
1
1
Right-justified, 16-bit
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