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| 型號： | PCM1851PJT |
| 英文描述： | 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA |
| 中文描述： | 24位，96千赫立體聲A / D轉(zhuǎn)換器6 × 2通道的MUX和PGA |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 370K |
| 代理商： | PCM1851PJT |
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PCM1850
PCM1851
SLES108
MARCH 2004
www.ti.com
13
SYSTEM CLOCK
The PCM1850/1851 supports 256 f
S
, 384 f
S
, 512 f
S,
and 768 f
S
as the system clock, where f
S
is the audio sampling
frequency. The system clock must be supplied on SCKI (pin 7).
The PCM1850/1851 has a system clock detection circuit which automatically senses if the system clock is operating at
256 f
S
, 384 f
S
, 512 f
S
or 768 f
S
in slave mode. In master mode, the system clock frequency must be selected by mode control
via the serial port. The 768-f
S
system clock is not available in master mode or for f
S
= 88.2 kHz and 96 kHz in the slave
mode. The system clock is divided into 128 f
S
and 64 f
S
automatically, and these frequencies are used to operate the digital
filter and the delta-sigma modulator, respectively.
Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 shows system clock
timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY (MHz)
256 f
S
8.192
11.2896
12.288
16.384
22.5792
24.576
384 f
S
12.288
16.9344
18.432
24.576
33.8688
36.864
512 f
S
16.384
22.5792
24.576
32.768
45.1584
49.152
768 f
S (1)
24.576
33.8688
36.864
49.152
—
—
32
44.1
48
64
88.2
96
(1)
Slave mode only
t
(SCKH)
SCKI
t
(SCKL)
2.0 V
0.8 V
H
L
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
SCKH
t
SCKL
System clock pulse duration, HIGH
8
ns
System clock pulse duration, LOW
8
ns
Figure 20. System Clock Timing
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