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參數(shù)資料
| 型號： | PCM1760P |
| 英文描述： | Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM |
| 中文描述： | 多位增強噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng) |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 201K |
| 代理商： | PCM1760P |
9
PCM1760P/U DF1760P/U
T
PCF
T
CSV
CAL
SDATA
/PD
T
PSF
T
PDW
T
PCR
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
Pulse Width of /PD Input
T
PDW
2
–
–
1/Fclk
Delay from /PD Input to
CAL Output
T
PCR
T
PCF
T
PSF
–
–
6
1/Fclk
Calibration Cycle Duration
–
4096
–
1/fs
Delay from /PD Input to S
DATA
L
Delay from Completion of
Calibration to SDATA Valid
FIGURE 3b. DF1760 Power Down and Offset Calibration.
–
–
6
1/Fclk
T
CSV
–
1
–
1/fs
SYSTEM CLOCK: 256fs
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
Low Level Duration
T
CLKL
T
CLKH
31
–
–
ns
High Level Duration
31
–
–
ns
T
CLKH
T
CLKL
2.0V
1.4V
0.8V
T
LH
T
HL
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
SCLK Frequency
F
SLK
T
SLKL
T
SLKH
T
SLR
32fs
48fs
64fs
–
Low Duration of FSCLK
100
–
–
ns
High Duration of FSCLK
100
–
–
ns
Delay from SCLK to L/R Edge
–70
–
70
ns
Delay from Falling Edge of
SCLK to SDATA Valid
T
DSS
–
–
50
ns
Delay from SCLK to FSYNC
Edge
T
SF
–70
–
0
ns
Delay from Rising Edge of
SCLK to SDATA Valid
T
DSV
100
–
–
ns
Delay from SDATA Valid to
Rising Edge of SCLK
T
SDR
100
–
–
ns
SCKL
SDATA
L/R
FSYNC
T
SLR
T
SDR
T
SF
T
DSS
T
DSV
T
SLKH
T
SLKL
FIGURE 3e. Timing of Slave Mode, DF1760.
FIGURE 3f. Power On and Mode Reset Timing.
APPLIES TO
MODE
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
(1)
Power on to PD
↑
T
PDW
2
1/fs
Master/Slave
PD
↑
to L/R
↑
(LRSC = “H”)
T
SP
–1
+1
1/Fclk
Slave
PD
↑
to L/R
↓
(LRSC = “L”)
T
SP
–1
+1
1/Fclk
Slave
NOTE: (1) fs: sampling rate. Fclk: system clock frequency.
T
PDW
T
PDW
T
SP
T
SP
Power
L/R
PD
<LRSC = “H”
T
PDW
T
PDW
T
SP
T
SP
Power
L/R
PD
<LRSC = “L”
SYSTEM CLOCK: 384fs
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
Low Level Duration
T
CLKL
T
CLKH
T
LH
T
HL
24
–
–
ns
High Level Duration
24
–
–
ns
Rise Time
–
–
6
ns
Fall Time
–
–
6
ns
FIGURE 3c. System Clock Timing Requirements of DF1760.
T
SDR
T
SF
T
DSS
SCLK
SDATA
L/R
FSYNC
T
SLR
T
DSV
T
DSS
T
DSV
T
SF
DESCRIPTION
NAME
MIN
TYP
MAX
UNITS
SCLK Frequency
F
SLK
–
64fs
–
SCLK Frequency Duty Cycle
–
50
–
%
FSYNC Frequency
F
SYNC
–
2fs
–
FSYNC Frequency Duty Cycle
–
50
–
%
Delay from SCLK to L/R Edge
T
SLR
–20
–
50
ns
Delay from Falling Edge of
SCLK to SDATA Valid
T
DSS
–
–
50
ns
Delay from SCLK to FSYNC
Edge
T
SF
–20
–
50
ns
Delay from Rising Edge of
SCLK to SDATA Valid
T
SDR
100
–
–
ns
Delay from SDATA Valid to
Rising Edge of SCLK
T
DSV
100
–
–
ns
FIGURE 3d. Output Timing of Master Mode, DF1760.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1760P-L | 功能描述:IC DUAL 20-BIT A/D CONV 28-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| PCM1760U | 制造商:Rochester Electronics LLC 功能描述:20BIT A/D CONVERTER - Bulk |
| PCM1760U/1K | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Multi-Bit Enhanced Noise Shaping 20-Bit |
| PCM1760U-L | 功能描述:IC DUAL 20-BIT A/D CONV 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| PCM1760U-L/1K | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Multi-Bit Enhanced Noise Shaping 20-Bit |
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