參數(shù)資料
型號: PCM1760P
英文描述: Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
中文描述: 多位增強(qiáng)噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng)
文件頁數(shù): 12/15頁
文件大?。?/td> 201K
代理商: PCM1760P
PCM1760P/U DF1760P/U
12
ANALOG INPUT
CONDITION
DIGITAL OUTPUT
+2.55V
+2.50V to +2.55V
+2.50V
0V
–2.50V
–2.83V to –2.85V
–2.85V
+Max Input
Overflow
+FSR
BPZ (Ideal)
–FSR
Overflow
–Max Input
72000H
70000H to 72000H
(2)
70000H
00000H
(1)
90000H
82FFFH to 82000H
(2)
82000H
NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over
70000H or under 82FFFH of digital output code.
TABLE I. Output Codes.
POWER SUPPLY SEQUENCING
The PCM1760 requires
±
V
CC
and
±
V
DD
power supplies. To
avoid any possibility of latch-up, the
±
V
CC
and
±
V
DD
power
should all be applied simultaneously or the +V
CC
and +V
DD
applied first followed by –V
CC
and –V
DD
.
FIGURE 10. Illustration of Offset Calibration.
+fs
BPZ
–fs
0V
+fs
–fs
ANALOG INPUT
V
OS
D
+fs
BPZ
–fs
0V
+fs
–fs
ANALOG INPUT
D
Analog Input
V
OS
PCM1760
DF1760
CAL
PD
V
OS
POWER-ON RESET AND MODE RESET
The timing requirements for POWER-ON RESET and
MODE RESET are shown in Figure 3f. The DF1760 re-
quires POWER-ON RESET when power is applied or re-
stored. MODE RESET is required when any of the follow-
ing has been changed: system clock, master/slave mode,
output data format, L/R clock, calibration after POWER-ON
in slave mode.
This reset should be done by holding the /PD input (pin 21)
low for more than 2/fs. Suggested reset circuits are given in
Figures 11, 12 and 13.
CLOCK INPUT
After power is applied to the DF1760, the system clock
should be provided continuously. The DF1760 employs a
dynamic logic architecture.
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