參數(shù)資料
型號(hào)： PCM1760
英文描述： Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
中文描述： 多位增強(qiáng)噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng)
文件頁(yè)數(shù)： 2/15頁(yè)
文件大小： 201K
代理商： PCM1760
PCM1760P/U DF1760P/U
2
SPECIFICATIONS
ELECTRICAL
At T
A
= +25
°
C,
±
V
CC
,
±
V
dd
= +5V, +V
DD
= +5V, f
S
= 48kHz and ext. components =
±
2% unless otherwise noted.
PCM1760/DF1760
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
20
Bits
ANALOG INPUT
Input Range
Input Impedance
R
IN
1 = 2.2k
R
IN
1 = 2.2k
±
2.5
R
IN
1
Vp-p
SAMPLING FREQUENCY
Cover Range of fs
Integrator Constants: Application
(1)
30
48
50
kHz
ACCURACY
Gain Error
Gain Mismatch
Bipolar Zero Error
Gain Drift
Bipolar Zero Drift
±
0.5
±
1.0
±
0.5
±
0.4
dB
dB
V
IN
= 0 at 20s After Power-On
0
°
C to +70
°
C
0
°
C to +70
°
C
% FSR
(2)
ppmfs/
°
C
ppmfs/
°
C
±
100
±
20
DYNAMIC CHARACTERISTICS
(4)
THD+N/(0dBFS)
P, U
P-L, U-L
P, U
P-L, U-L
P, U
P-L, U-L
P, U
P-L, U-L
P, U
P-L, U-L
f
IN
= 1kHz
–92
–90
–76
–76
–44
–44
108
108
110
110
±
0.1
98
–90
–88
–70
–70
–42
–42
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
THD+N/(–20dBFS)
f
IN
= 1kHz
THD+N/(–60dBFS)
f
IN
= 1kHz
Dynamic Range
f
IN
= 1kHz, V
IN
= –60dBFS, A Filter
104
104
108
106
SNR
V
IN
= 0, A Filter
Frequency Response
Channel Separation
f
IN
= 20kHz
f
IN
= 1kHz, A Filter
94
DIGITAL FILTER
Over Sample Rate
Ripple in Band
Stopband Attenuation –1
Stopband Attenuation –2
64
fs
dB
dB
dB
0 - 0.04535fs
0.5465fs - 63.4535fs
0.5465fs - 3.4535fs
±
0.0001
–94
–100
LOGIC INPUTS AND OUTPUTS
Logic Family Input
Frequency (System Clock 1)
Frequency (System Clock 2)
Duty Cycle (System Clock 1)
Duty Cycle (System Clock 2)
Data Clock Input
Logic Family Output
Data Clock Output
Data Coding
Data Bit Length
Data Format
Output Data Delay
TTL Level Compatible CMOS
12.288
18.432
50
50
48
CMOS
64
Two's Complement
20
Selectable
1.5
256fs
384fs
256fs
384fs
MHz
MHz
%
%
fs
40
45
32
60
55
64
fs
16
Bits
fs = 48kHz
ms
POWER SUPPLY REQUIREMENTS
Supply Voltage
±
V
CC
±
V
dd
+V
Supply Current
+I
CC
–I
CC
+I
dd
–I
DD
+I
DD
–1
+I
DD
–2
Power Consumption
PCM1760
PCM1760
DF1760
±
4.75
±
4.75
4.75
±
5.0
±
5.0
5.0
±
5.25
±
5.25
5.25
V
V
V
PCM1760
PCM1760
PCM1760
PCM1760
24
–30
12
–8
40
4
370
200
20
36
–45
18
–12
55
6.6
500
275
33
mA
mA
mA
mA
mA
mA
mW
mW
mW
DF1760, Normal Mode
DF1760, Power-Down Mode
PCM1760
DF1760, Normal Mode
DF1760, Power-Down Mode
TEMPERATURE RANGE
Operating
Storage
PCM1760/DF1760
PCM1760/DF1760
0
+25
+70
+125
°
C
°
C
–50
NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from
90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz
low-pass filter and 400Hz high-pass filter.
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