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參數(shù)資料
| 型號： | PCM1760 |
| 英文描述： | Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM |
| 中文描述： | 多位增強(qiáng)噪聲整形的20位模擬數(shù)字轉(zhuǎn)換系統(tǒng) |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 201K |
| 代理商： | PCM1760 |
11
PCM1760P/U DF1760P/U
OUTPUT TONE ELIMINATION
When the sampling frequency (fs) is between 40kHz and 50 kHz
and the L/R relative offset voltage (
Vs) is less than or equal to
0.05% of full scale range, the PCM1760 may output a tone
similar to an idle tone. This tone is very low and its frequency
depends on the input L/R relative offset voltage,
Vs. This
tone never occurs when the sampling frequency (fs) is 32kHz.
To avoid this tone, the offset voltage should be summed
using an amplifier, buffer, active low pass filter, etc., to
cause the input L/R relative offset voltage (
Vs) to be
greater than 0.05% of full scale range.
It is recommended that:
(A) Sum offset at both L/R channels
Lch: V
IL
= –20mV
±
10%
Rch: V
IR
= +10mV
±
10%
(B) Sum offset at L channel
Lch: V
IL
= –30mV
±
10%
Rch: V
IR
=
±
1mV (by a precircuit)
When FSR = 5V (
±
2.5V).
Figure 8 shows an application circuit for summing the offset
at both L/R channels.
Alternately, Figure 9 shows an application circuit for use
when fs = 48kHz which changes the external integrator
circuit of the PCM1760.
MODULATOR COMPONENTS
AND SAMPLING FREQUENCY
The PCM1760/DF1760 are capable to 30kHz to 50kHz fs
sampling frequency by condition with external components
value which are shown in Basic Connection Diagram.
The characteristics of the modulator’s integrator can be set
by external components. The values in the block diagram on
page five are recommended for optimized performance.
Low leakage, low voltage coefficient capacitors are recom-
mended for integration capacitors.
The tolerance of external components should be better than
±
2%.
FIGURE 8. Application Example to Eliminate the Tone
(offset voltage implementation for both chan-
nels).
OFFSET ERROR CALIBRATION
The offset voltage of the PCM1760 and the input stage of
the system can be compensated by using the calibration
mode of the DF1760. Offset calibration is shown in Figure
10. An optional analog switch is driven by a CAL output of
the DF1760. The PD input of the DF1760 is used to initiate
the calibration cycle.
ANALOG INPUT AND DIGITAL OUTPUT
Ideal output digital code range for 20-bit resolution is from
8000H (–Full Scale) to 7FFFFH (+Full Scale).
The DF1760, combined with 70000H (
±
FSR) of the
PCM1760, produces a digital output code range at
±
FSR
input of 90000H (–FSR).
The relationship between analog input and digital output is
shown in Table I.
C
1
C
2
CZ
1
11
12
13
14
RT
1
RZ
1
R
IN1
R
IN2
C
3
C
4
RT
2
RZ
2
PCM1760
OP1
OP2
R
IN1
= 2.2k
RT
= 2.2k
C
1
, C
, C
3
, C
4
= 1200pF
RT
1
= 470
RZ
1
= 470
CZ
1
= 220pF
R
IN2
= 1.3k
RZ
2
= 910
FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz).
2.2k
2.2k
PCM1760
11
4
R
IN
1-L
R
IN
1-R
V
IR
= +10mV ±10%
V
IL
= –20mV ±10%
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| PCM1760U | 制造商:Rochester Electronics LLC 功能描述:20BIT A/D CONVERTER - Bulk |
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