參數(shù)資料
型號(hào): PCM1718E
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 172K
代理商: PCM1718E
9
PCM1718E
FIGURE 10. 5-Level
Σ
Modulator Block Diagram.
POWER SUPPLY
CONNECTIONS
PCM1718 has two power supply connections: digital (V
DD
)
and analog (V
CC
). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condi-
tion, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
An application circuit to avoid a latch-up condition is shown
in Figure 9.
DGND
AGND
V
DD
V
CC
Digital
Power Supply
Analog
Power Supply
FIGURE 9. Latch-up Prevention Circuit.
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 8 for optimal values of bypass
capacitors.
THEORY OF OPERATION
The delta-sigma section of PCM1718 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 10. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 48fs for
a 384fs system clock, and 64fs for a 256fs system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 11.
20
0
–20
–40
–60
–80
–100
–120
–140
–160
3rd-ORDER
Σ
MODULATOR
Frequency (kHz)
0
5
10
15
20
G
25
FIGURE 11. Quantization Noise Spectrum.
Out
48fs
(384fs)
64fs
(256fs)
In
8fs
18-Bit
+
+
+
4
3
2
1
0
5-level Quantizer
+
+
Z
–1
+
+
Z
–1
+
+
Z
–1
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