參數(shù)資料
型號(hào): PCM1718E
英文描述: Stereo Audio DIGITAL-TO-ANALOG CONVERTER
中文描述: 立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 6/11頁
文件大?。?/td> 172K
代理商: PCM1718E
6
PCM1718E
C
1
C
2
C
1
, C
2
= typ 22pF
Internal System Clock
XTI
X’tal
XTO
PCM1718E
CLKO
External Clock
Internal System Clock
XTI
XTO
PCM1718E
EXTERNAL CLOCK INPUT
XTO pin = No Connection
CRYSTAL RESONATOR CONNECTION
CLKO
SYSTEM CLOCK
The system clock for PCM1718 must be either 256fs or
384fs, where fs is the audio sampling frequency (typically
32kHz, 44.1kHz, or 48kHz). The system clock is used to
operate the digital filter and the modulator.
The system clock can be either a crystal oscillator placed
between XTI (pin 1) and XTO (pin 20), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1718 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256fs or
384fs. The system clock should be synchronized with LRCIN
(pin 4) clock. LRCIN (left-right clock) operates at the
sampling frequency fs. In the event these clocks are not
synchronized, PCM1718 can compensate for the phase dif-
ference internally. If the phase difference between left-right
and system clocks is greater than 6 bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1718 on pins 4, 5,
and 6—LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1718 can accept both normal and
I
2
S data formats. Normal data format is MSB first, two’s
complement, right-justified. I
2
S data is compatible with
Philips serial data protocol. Figures 3 and 4 illustrate the
input data formats.
FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.
FIGURE 2. External Clock Timing Requirements.
t
XTIH
t
XTIL
1/256fs or 1/384fs
64% OF V
DD
28% OF V
DD
External System Clock High
External System Clock Low
t
XTIH
t
XTIL
10ns (min)
10ns (min)
FUNCTION
CONTROL PIN
Data Input Format
Normal
I
2
S
De-emphasis
32kHz
44.1kHz
48kHz
Soft Mute
Reset
FORMAT (Pin 14)
DM0, DM1 (Pins 16, 17)
MUTE (Pin 18)
RSTB (Pin 15)
FUNCTIONAL CONTROLS
PCM1718 allows the user to control the input data format,
soft mute, and digital de-emphasis frequency. Table I illus-
trates the selectable functions:
TABLE I. Selectable Functions.
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