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參數(shù)資料
| 型號： | PCM1718E |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 立體聲音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 172K |
| 代理商： | PCM1718E |
11
PCM1718E
FIGURE 15. Test Block Diagram.
TEST CONDITIONS
Figure 15 illustrates the actual test conditions applied to
PCM1718 in production. The 11th-order filter is necessary
in the production environment for the removal of noise
resulting from the relatively long physical distance between
the unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 14 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11th-
order filter is used. For cost-sensitive applications, a single
RC filter, as shown in Figure 18, may be adequate.
EVALUATION FIXTURES
DEM-PCM1718
This evaluation fixture is primarily intended for quick evalu-
ation of the PCM1718’s performance. DEM-PCM1718 can
accept either an external clock or a user-installed crystal
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1718 does not contain a receiver chip
or an external low pass filter. DEM-PCM1718 requires a
single +2.7V to +5V power supply.
OUT-OF-BAND NOISE CONSIDERATIONS
Delta-sigma DACs are by nature very sensitive to jitter on
the master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons delta-
sigma DACs are prone to jitter sensitivity is the large
quantization noise when the modulator can only achieve two
discrete output levels (0 or 1). The multi-level delta-sigma
DAC has improved theoretical SNR because of multiple
output states. This reduces sensitivity to jitter. Figure 16
contrasts jitter sensitivity between a one-bit PWM type DAC
and multi-level delta-sigma DAC. The data was derived
using a simulator, where clock jitter could be completely
synthesized.
PGA
Digital
Lch
Rch
DEM-
PCM1718
CD
Player
DAI
11th-order
LPF
THD
Meter
0dB/60dB
30KHz LPF on
Through
For test of S/N ratio and Dynamic Range, A-filter ON.
Test Disk
Shibasoku #725
0
100
200
300
400
500
600
110
105
100
95
90
85
80
75
70
65
60
D
Clock Jitter (ps)
Multi-level
PWM
FIGURE 16. Simulation Results of Clock Jitter Sensitivity.
FIGURE 17. Simulation Method for Clock Jitter.
2
1
0
–1
2
48fs
14.4ps
1k
1800pF
PCM1718
Output
f
C
= 88kHz
FIGURE 18. RC Output Filter.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM1718E/2K | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC SoundPlus Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1718E/2KG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC SoundPlus Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1718EG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PCM1718EG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC SoundPlus Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1719 | 制造商:BB 制造商全稱:BB 功能描述:Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
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