參數(shù)資料
型號(hào)： PCM1605Y
英文描述： 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
中文描述： 24位192kHz采樣,6 -通道，增強(qiáng)的多級(jí)，Δ-Σ數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 263K
代理商： PCM1605Y
5
PCM1604, PCM1605
PIN
NAME
I/O
DESCRIPTION
1
ZERO1/GPO1
O
Zero Data Flag for V
OUT
1. Can also be used as GPO pin.
Zero Data Flag for V
OUT
2. Can also be used as GPO pin.
Zero Data Flag for V
OUT
3. Can also be used as GPO pin.
Zero Data Flag for V
OUT
4. Can also be used as GPO pin.
Zero Data Flag for V
OUT
5. Can also be used as GPO pin.
Zero Data Flag for V
OUT
6. Can also be used as GPO pin.
Analog Ground
2
ZERO2/GPO2
O
3
ZERO3/GPO3
O
4
ZERO4/GPO4
O
5
ZERO5/GPO5
O
6
ZERO6/GPO6
O
7
AGND
—
8
V
CC
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
COM
2
V
COM
1
AGND6
—
Analog Power Supply, +5V
9
O
Voltage Output for Audio Signal Corresponding to Rch on DATA3.
10
O
Voltage Output for Audio Signal Corresponding to Lch on DATA3.
11
O
Voltage Output for Audio Signal Corresponding to Rch on DATA2.
12
O
Voltage Output for Audio Signal Corresponding to Lch on DATA2.
13
O
Voltage Output for Audio Signal Corresponding to Rch on DATA1.
14
O
Voltage Output for Audio Signal Corresponding to Lch on DATA1.
Common Voltage Output. This pin should be bypassed with a 10
μ
F capacitor to AGND.
Common Voltage Output. This pin should be bypassed with a 10
μ
F capacitor to AGND.
Analog Ground
15
O
16
O
17
—
18
V
CC
6
AGND5
—
Analog Power Supply, +5V
19
—
Analog Ground
20
V
CC
5
AGND4
—
Analog Power Supply, +5V
21
—
Analog Ground
22
V
CC
4
AGND3
—
Analog Power Supply, +5V
23
—
Analog Ground
24
V
CC
3
AGND2
—
Analog Power Supply, +5V
25
—
Analog Ground
26
V
CC
2
AGND1
—
Analog Power Supply, +5V
27
—
Analog Ground
28
V
CC
1
AGND0
—
Analog Power Supply, +5V
29
—
Analog Ground
30
V
CC
0
NC
—
Analog Power Supply, +5V
31
—
No Connection. Must be open.
32
NC
—
No Connection. Must be open.
33
MDO
O
Serial Data Output for Function Register Control Port
(3)
34
MDI
I
Serial Data Input for Function Register Control Port
(1)
35
MC
I
Shift Clock for Function Register Control Port
(1)
36
ML
I
Latch Enable for Function Register Control Port
(1)
37
RST
I
System Reset, Active LOW
(1)
38
SCKI
I
System Clock In. Input frequency is 128, 192, 256, 384, 512 or 768f
S
.
(2)
Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768f
S
or one-half of 128, 192, 256, 384, 512,
or 768f
S.
Shift Clock Input for Serial Audio Data
(2)
39
SCKO
O
40
BCK
I
41
LRCK
I
Left and Right Clock Input. This clock is equal to the sampling rate, f
S
.
(2)
Test Pin. This pin should be connected to DGND.
(1)
42
TEST
—
43
V
DD
DGND
—
Digital Power Supply, +3.3V
44
—
Digital Ground for +3.3V
45
DATA1
I
Serial Audio Data Input for V
OUT
1 and V
OUT
2
(2)
Serial Audio Data Input for V
OUT
3 and V
OUT
4
(2)
Serial Audio Data Input for V
OUT
5 and V
OUT
6
(2)
Zero Data Flag. Logical “AND” of ZERO1 through ZERO6.
46
DATA2
I
47
DATA3
I
48
ZEROA
O
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
PIN ASSIGNMENTS
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