參數(shù)資料
型號(hào): PCM1605Y
英文描述: 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,6 -通道,增強(qiáng)的多級(jí),Δ-Σ數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 21/32頁
文件大?。?/td> 263K
代理商: PCM1605Y
21
PCM1604, PCM1605
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER 9
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
FLT0
CLKD
CLKE
FMT2
FMT1
FMT0
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
FLT0
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 000
B
FLT0 = 0
FLT0 = 1
Sharp Roll-Off (default)
Slow Roll-Off
Bit FLT0 allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll-
off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical
Performance Curves section of this data sheet.
CLKD
SCKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CLKD = 0
CLKD = 1
Full Rate, f
SCKO
= f
SCKI
(default)
Half Rate, f
SCKO
= f
SCKI
/2
The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.
CLKE
SCKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
SCKO Enabled (default)
SCKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it will
output either a full or half rate clock, based upon the setting of the CLKD bit.
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000
B
FMT[2:0]
Audio Data Format Selection
000
001
010
011
100
101
110
111
24-Bit Standard Format, Right-Justified Data (default)
20-Bit Standard Format, Right-Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I
2
S Format, 16- to 24-bits
Left-Justified Format, 16- to 24-Bits
Reserved
Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
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參數(shù)描述
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