參數(shù)資料
型號: PCM1605Y
英文描述: 24-Bit, 192kHz Sampling,6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
中文描述: 24位192kHz采樣,6 -通道,增強的多級,Δ-Σ數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 17/32頁
文件大?。?/td> 263K
代理商: PCM1605Y
17
PCM1604, PCM1605
MODE CONTROL REGISTERS
User-Programmable Mode Controls
The PCM1604 includes a number of user-programmable
functions which are accessed via control registers. The
registers are programmed using the Serial Control Interface
which was previously discussed in this data sheet. Table III
lists the available mode control functions, along with their
reset default conditions and associated register index.
FUNCTION
RESET DEFAULT
CONTROL REGISTER
INDEX, IDX[6:0]
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
Digital Attenuation Load Control
Digital Attenuation Rate Select
Soft Mute Control
DAC 1-6 Operation Control
Infinite Zero Detect Mute
Audio Data Format Control
Digital Filter Roll-Off Control
SCKO Frequency Selection
SCKO Output Enable
De-Emphasis Function Control
De-Emphasis Sample Rate Selection
Output Phase Reversal
Read Register Index Control
Read Auto-Increment Control
General Purpose Output Enable
General Purpose Output Bits (GPO1-GPO6)
Oversampling Rate Control
0dB, No Attenuation
Data Load Disabled
2/f
S
Mute Disabled
DAC 1-6 Enabled
Disabled
24-Bit Standard Format
Sharp Roll-Off
Full Rate (= f
SCKI
)
SCKO Enabled
De-Emphasis Disabled
44.1kHz
Disabled
REG[6:0] = 01
H
Auto-Increment Disabled
Zero Flags Enabled
Disabled
64x (32x for 192kHz)
1 through 6
7
7
7
8
8
9
9
9
9
10
10
10
11
11
12
12
12
01
H
- 07
H
07
H
07
H
07
H
08
H
08
H
09
H
09
H
09
H
09
H
0A
H
0A
H
0A
H
0B
H
0B
H
0C
H
0C
H
0C
H
TABLE III. User-Programmable Mode Controls.
TABLE IV. Mode Control Register Map.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Register 1
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
Register 3
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT37
AT36
AT35
AT34
AT33
AT32
AT31
AT30
Register 4
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT47
AT46
AT45
AT44
AT43
AT42
AT41
AT40
Register 5
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT57
AT56
AT55
AT54
AT53
AT52
AT51
AT50
Register 6
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT67
AT66
AT65
AT64
AT63
AT62
AT61
AT60
Register 7
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
ATLD
ATTS
MUT6
MUT5
MUT4
MUT3
MUT2 MUT1
Register 8
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
INZD
DAC6
DAC5
DAC4
DAC3
DAC2 DAC1
Register 9
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
FLT0
CLKD
CLKE
FMT2
FMT1
FMT0
Register 10
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
res
REV
DMF1
DMF0
DM56
DM34
DM12
Register 11
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1 REG0
Register 12
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
OVER
GPOE
GPO6
GPO5
GPO4
GPO3
GPO2 GPO1
Register Map
The mode control register map is shown in Table IV. Each
register includes a R/W bit, which determines whether a
register read (R/W =1) or write (R/W = 0) operation is
performed. Each register also includes an index (or address)
indicated by the IDX[6:0] bits.
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