參數(shù)資料
型號: PCKV857
廠商: NXP Semiconductors N.V.
英文描述: 70-190 MHz differential 1:10 clock driver
中文描述: 70-190兆赫1:10差動時鐘驅(qū)動器
文件頁數(shù): 6/12頁
文件大小: 84K
代理商: PCKV857
Philips Semiconductors
Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2001 Jun 12
6
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
2.5 ns; C
L
= 50 pF; R
L
= 1 k
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
UNIT
MIN
TYP
MAX
t
(O)
t
SK(O)
t
SLR(O)
t
JIT(PER)
t
JIT(CC)
t
JIT(HPER)
Static phase offset
Figure 1
–150
0
150
ps
Output clock skew
Figure 2
75
ps
Output clock skew rate
Figure 3
1
2
V/ns
Jitter (period)
Figure 4
f
O
= 67 MHz to 200 MHz
f
O
= 67 MHz to 200 MHz
–75
75
ps
Jitter (cycle-to-cycle)
Figure 5
–75
75
ps
Half-period jitter
Figure 6
–100
100
ps
t
PLH1
Low to high level
propagation delay
Test mode/CLK to any
output
3.7
ns
t
PHL1
High to low level
propagation delay
Test mode/CLK to any
output
3.7
ns
NOTE:
1. Refers to transition of noninverting output.
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00688
S
S
S
S
S
S
S
S
S
SSTL16877
or
SSTV16857
PCKV857
FRONT SIDE
SSTL16877
or
SSTV16857
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