參數(shù)資料
型號(hào)： PCKV857
廠商： NXP Semiconductors N.V.
英文描述： 70-190 MHz differential 1:10 clock driver
中文描述： 70-190兆赫1:10差動(dòng)時(shí)鐘驅(qū)動(dòng)器
文件頁(yè)數(shù)： 2/12頁(yè)
文件大小： 84K
代理商： PCKV857
Philips Semiconductors
Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2
2001 Jun 12
853–2242 26485
FEATURES
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
1-to-10 differential clock distribution
Very low skew (
<
100 ps) and jitter (
<
100 ps)
Operation from 2.2 V to 2.7 V AV
DD
and 2.3 V to 2.7 V V
DD
SSTL_2 interface clock inputs and outputs
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Full DDR solution provided when used with SSTL16877 or
SSTV16857
See PCKV856 for I
2
C capable clock driver
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V V
DD
and 2.5 V AV
DD
operation and
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FB
OUT
, FB
OUT
) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FB
IN
, FB
IN
), and the analog
power input (AV
DD
). When PWRDWN is high, the outputs switch in
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AV
DD
is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70
°
C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
GND
Y
0
Y
0
V
DDQ
Y
1
Y
1
GND
Y
2
Y
2
GND
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
Y
3
Y
3
V
DDQ
Y
4
Y
4
GND
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
PWRDWN
FB
IN
FB
IN
V
DDQ
FB
OUT
FB
OUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
SW00691
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic TSSOP
0 to +70
°
C
PCKV857DGG
SOT362-1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCKV857A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:100-250 MHz differential 1:10 clock driver
PCKV857ADGG 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:100-250 MHz differential 1:10 clock driver
PCKV857ADGG,512 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCKV857ADGG,518 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PCKV857ADGV 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:100-250 MHz differential 1:10 clock driver
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