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參數(shù)資料
| 型號： | PCK953 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver |
| 中文描述： | 50-125兆赫PECL的輸入/ 9 CMOS輸出3.3伏PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 71K |
| 代理商： | PCK953 |
Philips Semiconductors
Product specification
PCK953
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
2001 Feb 08
6
At the load end, the voltage will double due to the near unity
reflection coefficient, to 2.62 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round-trip delay (in this
case 4.0 ns).
SW00630
OutB
t
D
= 3.9386
V
3.0
2.5
2.0
1.5
1.0
0.5
0
TIME (ns)
2
4
6
8
10
12
14
In
OutA
t
D
= 3.8956
Figure 3. Single versus dual waveforms
Since this step is well above the threshold region, it will not cause
any false clock triggering, however designers may be uncomfortable
with unwanted reflections on the line. To better match the
impedances when driving multiple lines, the situation in Figure 4
should be used. In this case, the series terminating resistors are
reduced such that when the parallel combination is added to the
output buffer impedance, the line impedance is perfectly matched.
SW00629
PCK953
OUTPUT
BUFFER
14
R
S
= 22
Z
O
= 50
R
S
= 22
Z
O
= 50
14
+ 22
22
= 50
50
25
= 25
Figure 4. Optimized dual line termination
SPICE level output buffer models are available for engineers who
want to simulate their specific interconnect schemes. In addition, IV
characteristics are in the process of being generated to support the
other board-level simulators in general use.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK953BD | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL IP/1.8SDRAM CKDR RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,118 | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,128 | 功能描述:鎖相環(huán) - PLL 50-125MHZ 1:8 SDRAM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,157 | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD/01,118 | 制造商:NXP Semiconductors 功能描述: |
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