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參數資料
| 型號： | PCK953 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver |
| 中文描述： | 50-125兆赫PECL的輸入/ 9 CMOS輸出3.3伏PLL時鐘驅動器 |
| 文件頁數： | 4/8頁 |
| 文件大小： | 71K |
| 代理商： | PCK953 |
Philips Semiconductors
Product specification
PCK953
50–125 MHz PECL input/CMOS output
3.3 V PLL clock driver
2001 Feb 08
4
DC CHARACTERISTICS
T
amb
= 0 to 70
°
C; V
CC
= 3.3 V
±
5%
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
V
IH
V
IL
V
p-p
V
CMR
V
OH
V
OL
I
IN
C
IN
C
PD
I
CC
I
CCPLL
Input HIGH voltage LVCMOS inputs
2.0
—
3.6
V
Input LOW voltage LVCMOS inputs
—
—
0.8
V
Peak-to-peak input voltage
PECL_CLK
300
—
1000
mV
Common mode range
PECL_CLK
Note 1
V
CC
–1.5
2.4
—
V
CC
–0.6
—
mV
Output HIGH voltage
I
OH
= –20 mA;
2
I
OL
= 20 mA;
2
—
V
Output LOW voltage
—
—
0.5
±
75
4
V
μ
A
pF
Input current
—
—
Input capacitance
—
—
Power dissipation capacitance
per output
—
25
—
pF
Maximum quiescent supply current
All V
CC
pins
V
CCA
pin only
—
9
20
mA
Maximum PLL supply current
—
9
20
mA
NOTES:
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within
the V
CMR
range and the input swing lies within the V
PP
specification.
2. The PCK953 outputs can drive series or parallel terminated 50
(or 50
to V
CC
/2) transmission lines on the incident edge (see
Applications info section).
PLL INPUT REFERENCE CHARACTERISTICS
T
amb
= 0 to 70
°
C
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
f
ref
f
refDC
Reference input frequency
20
125
MHz
Reference input duty cycle
25
75
%
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
AC CHARACTERISTICS
T
amb
= 0 to 70
°
C; V
CC
= 3.3 V
±
5%
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
t
r
, t
f
t
pw
t
sk(O)
f
VCO
f
MAX
Output rise/fall time
0.8 V to 2.0 V
0.30
0.55
0.8
ns
Output duty cycle
45
50
55
%
Output-to–output skews (relative to QFB)
—
—
100
ps
PLL VCO lock range
200
—
500
MHz
Maximum output frequency
PLL mode
VCO_SEL = 1
VCO_SEL = 0
20
50
—
125
225
125
MHz
MHz
MHz
ps
Bypass mode
t
pd
(lock)
t
pd
(by-
pass)
t
PLZ-HZ
t
PZL
t
jitter
t
lock
NOTE:
1. X will be targeted for 0 ns, but may vary from target by
±
150 ps based on characterization of silicon.
Input to EXT_FB delay (with PLL locked)
f
ref
= 50 MHz
PLL bypassed
–75
—
Input to Q delay
3
5.2
7
ns
Output disable time
—
—
7
ns
Output enable time
—
—
6
ns
Cycle-to-cycle jitter (peak-to-peak)
—
55
100
ps
Maximum PLL lock time
—
0.01
10
ms
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCK953BD | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL IP/1.8SDRAM CKDR RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,118 | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,128 | 功能描述:鎖相環(huán) - PLL 50-125MHZ 1:8 SDRAM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD,157 | 功能描述:鎖相環(huán) - PLL 50-125MHZPECL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK953BD/01,118 | 制造商:NXP Semiconductors 功能描述: |
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