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參數(shù)資料
| 型號(hào)： | PCI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 47/192頁(yè) |
| 文件大?。?/td> | 1551K |
| 代理商： | PCI9080 |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 38
Version 1.02
3.13.1 Inbound Messages
Inbound messages reside in a pool of message frames
(minimum 64-byte frames) allocated in shared local bus
(IOP) memory. The inbound message queue is
comprised of a pair of rotating FIFOs implemented in
local memory. Inbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in local memory. Inbound Post List FIFO holds
the MFA of all currently-posted messages.
The inbound circular FIFOs are accessed by external
PCI agents through Inbound Queue Port location in the
PCI address space. Inbound Queue Port, when read by
an external PCI agent, returns the Inbound Free List
FIFO MFA. An external PCI agent places a message
frame into the Inbound Post List FIFO by writing its MFA
to the inbound queue port location.
3.13.2 Outbound Messages
Outbound messages reside in a pool of message frames
(minimum 64-byte frames) allocated in shared PCI bus
(Host System) memory. The outbound message queue
is comprised of a pair of rotating FIFOs implemented in
local memory. Outbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in system memory. Outbound Post List FIFO
holds the MFA of all currently posted messages.
The outbound circular FIFOs are accessed by external
PCI agents through the Outbound Queue Port location in
the PCI address space. Outbound Queue Port, when
read by an external PCI agent, returns the Outbound
Post List FIFO MFA. An external PCI agent places free
message frames into the Outbound Free List FIFO by
writing the free MFA into the Outbound Queue Port
location.
Memory for the circular FIFOs themselves must be
allocated in local (IOP) memory. The queues base
address is contained in Queue Base Address Register
(QBAR). Each FIFO entry is a 32 bit data value. Each
read and write of the queue must be a single 32-bit
access.
The circular FIFOs range in size from 4K entries to 64K
entries. All four FIFOs must be the same size and
contiguous. Therefore, the total amount of local memory
needed for circular FIFOs ranges from 64 KB to 1 MB.
FIFO size is specified in the Messaging Queue
Configuration Register (MQCR) (refer to Table 4-79).
The starting address of each FIFO is based on the
Queue base Address and the FIFO Size, as listed in
Table 3-7.
Table 3-7. Queue Starting Address
FIFO
Starting Address
Inbound Free List
QBAR
Inbound Post List
QBAR + (1 * FIFO Size)
Outbound Post List
QBAR + (2 * FIFO Size)
Outbound Free List
QBAR + (3 * FIFO Size)
3.13.3 I
2
O Pointer Management
FIFOs always reside in shared local (IOP) memory and
are allocated and initialized by the IOP. Before enabling
I
2
O (Messaging Queue Configuration Register bit 0 set
to 1), the local processor must initialize the Inbound Post
and Free Head Pointer Registers, the Inbound Post and
Free Tail Pointer Registers, the Outbound Post and Free
Head Pointer Registers, and the Outbound Post and
Free Tail Pointer Registers with the initial offset
according to the configured FIFO size. Messaging Unit
automatically adds the Queue Base Address to offset in
each head and tail pointer register. The software can
then enable I
2
O. After initialization, the local software
should not write to the pointers managed by the MU
hardware.
The empty flags are set if the queues are disabled
(MQCR bit 0 = 0) and head and tail pointers are equal.
This occurs independently of how the head and tail
pointers are set.
An empty flag is cleared, signifying not empty, only if the
queues are enabled and pointers become not equal.
If an empty flag is cleared and the queues are enabled,
the empty flag will only be set if the tail pointer is
incremented and head and tail pointers become equal.
Full flags are always cleared when the queues are
disabled or the head and tail pointers are not equal.
A full flag is set when the queues are enabled, the head
pointer is incremented, and the head and tail pointers
become equal.
Each circular FIFO has a head pointer and a tail pointer,
which are offsets from the Queue Base Address. Writes
to a FIFO occur at the head of the FIFO and reads occur
from the tail. The head and tail pointers are incremented
by either the local processor or the MU hardware. The
unit that writes to the FIFO also maintains the pointer.
The pointers are incremented after FIFO access. Both
pointers wrap around to the first address of the circular
FIFO when they reach the FIFO size, so that the head
and tail pointers “chase” each other around and around
in the circular FIFO. MU wraps the pointers automatically
for the pointers that it maintains. IOP software must wrap
the pointers that it maintains. Whenever they are equal,
the FIFO is empty. To prevent overflow conditions, I
2
O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9080 REV3 | 制造商:PLX TECH 功能描述: |
| PCI9080-3 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI I2O Compatible PCI BUS MASTER I/O CHIP RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9080-3 G | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32Bit Master Chip RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9080-3G | 制造商:PLX Technology 功能描述: |
| PCI-9111DG | 功能描述:數(shù)據(jù)記錄與采集 100KS/s 12BIT MULTI-FUNCTION CARD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
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