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參數(shù)資料
| 型號(hào)： | PCI1620GHK |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 66/164頁(yè) |
| 文件大?。?/td> | 720K |
| 代理商： | PCI1620GHK |
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3
–
24
The seven power-management states of PCI functions are:
D0-uninitialized
–
Before device configuration, device not fully functional
D0-active
–
Fully functional state
D1
–
Low-power state
D2
–
Low-power state
D3
hot
–
Low-power state. Transition state before D3
cold
D3
cold
–
PME signal-generation capable. Main power is removed and VAUX is available.
D3
off
–
No power and completely non-functional
NOTE 1: In the D0-uninitialized state, the PCI1620 does not generate PME and/or interrupts. When the IO_EN and MEM_EN bits (bits 0 and
1) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI1620 switches the state to D0-active. Transition from
D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the
D0-uninitialized state immediately.
NOTE 2: The PWR_STATE bits (bits 0
–
1) of the power-management control/status register (PCI offset A4h, see Section 4.46) only code for four
power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller
is not accessible in the D3cold or D3off state.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function should support
four power-management operations. These operations are:
Capabilities reporting
Power status reporting
Setting the power state
System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. Each item in the list consists
of 2 bytes. The first byte of each capability register block is required to be a unique ID of that capability, and the second
byte is a pointer to the next capability item in the list. The next-item pointer of the last item in the list must be set to
0. For the PCI1620, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is located
at PCI offset 14h, and points to the capabilities ID register (PCI offset A0h, see Section 4.43). The capabilities ID
register contains a value of 01h, which is the unique ID assigned to PCI power management. Because PCI power
management is the only capability in the PCI1620, the next byte, in the next item pointer register (PCI offset A1h, see
Section 4.44) is 0. The registers following the next item pointer are specific to the capability of the function. The PCI
power-management capability implements the register block outlined in Table 3
–
16.
Table 3
–
16. Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
A0h
Data
Power-management
control/status register bridge
support extensions
Power-management control/status (CSR)
A4h
The power management capabilities register (PCI offset A2h, see Section 4.45) is a static read-only register that
provides information on the capabilities of the function related to power management. The power-management
control/status register (PCI offset A4h, see Section 4.46) enables control of power-management states and
enables/monitors power-management events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the
PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges
.
3.7.9
CardBus Bridge Power Management
The
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the
PCI Bus Power
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
| PCI9054AB50BI | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
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