參數(shù)資料
型號(hào)： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 160/164頁
文件大?。?/td> 720K
代理商： PCI1620GHK
8
–
8
8.10 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, Memory Cycles (for 100-ns Common Memory) (see
Note 8 and Figure 8
–
5)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
tsu
tsu
tsu
tpd
tw
th
th
tsu
th
th
tsu
th
NOTE 6: These times are dependent on the register settings associated with ISA wait states and data size. They are also dependent on cycle
type (read/write, memory/I/O) and WAIT from PC Card. The times listed here represent absolute minimums (the times that would be
observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.
Setup time, CE1 and CE2 before WE/OE low
T1
60
ns
Setup time, CA25
–
CA0 before WE/OE low
T2
tsu(A)+2PCLK
ns
Setup time, REG before WE/OE low
T3
90
ns
Propagation delay time, WE/OE low to WAIT low
T4
ns
Pulse duration, WE/OE low
T5
200
ns
Hold time, WE/OE low after WAIT high
T6
ns
Hold time, CE1 and CE2 after WE/OE high
T7
120
ns
Setup time (read), CDATA15
–
CDATA0 valid before OE high
T8
ns
Hold time (read), CDATA15
–
CDATA0 valid after OE high
T9
0
ns
Hold time, CA25
–
CA0 and REG after WE/OE high
T10
th(A)+1PCLK
ns
Setup time (write), CDATA15
–
CDATA0 valid before WE low
T11
60
ns
Hold time (write), CDATA15
–
CDATA0 valid after WE low
T12
240
ns
8.11 Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature, I/O Cycles (see Figure 8
–
6)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
tsu
tsu
tsu
tpd
tpd
tw
th
th
th
th
tsu
th
tsu
th
Setup time, REG before IORD/IOWR low
T13
60
ns
Setup time, CE1 and CE2 before IORD/IOWR low
T14
60
ns
Setup time, CA25
–
CA0 valid before IORD/IOWR low
T15
tsu(A)+2PCLK
ns
Propagation delay time, IOIS16 low after CA25
–
CA0 valid
T16
35
ns
Propagation delay time, IORD low to WAIT low
T17
35
ns
Pulse duration, IORD/IOWR low
T18
TcA
ns
Hold time, IORD low after WAIT high
T19
ns
Hold time, REG low after IORD high
T20
0
ns
Hold time, CE1 and CE2 after IORD/IOWR high
T21
120
ns
Hold time, CA25
–
CA0 after IORD/IOWR high
T22
th(A)+1PCLK
ns
Setup time (read), CDATA15
–
CDATA0 valid before IORD high
T23
10
ns
Hold time (read), CDATA15
–
CDATA0 valid after IORD high
T24
0
ns
Setup time (write), CDATA15
–
CDATA0 valid before IOWR low
T25
90
ns
Hold time (write), CDATA15
–
CDATA0 valid after IOWR high
T26
90
ns
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
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PCI1620ZHK 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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