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| 型號(hào)： | PCF8890 |
| 英文描述： | 240 + 1 outputs TFT LCD gate driver |
| 中文描述： | 240 1輸出TFT液晶柵極驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 54/76頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCF8890 |
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2002 Aug 16
54
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
Notes
1.
All timing values are valid within the operating ambient temperature and supply voltage ranges and are referred to
V
IL
and V
IH
with an input voltage swing of V
SS1
to V
DD1
.
Not directly observable at any pin.
C
b
= total capacitance of one bus line in pF.
The input signal rise time and fall time (t
r
and t
f
) are specified at 15 ns or less. When the cycle time is used at
high-speed, the specification is t
r
+ t
f
≤
(T
CYC
t
CCLW
t
CCHW
) or t
r
+ t
f
≤
(T
CYC
t
CCLR
t
CCHR
).
The system cycle time can be derated for different values of V
DD1
. For V
DD1
< 2.5 V the system cycle time can be
calculated as follows:
at V
DD1
= 2.5 V, f
CYC(2.5)
= 6.25 MHz and
f = 0.44 MHz/V then
The input signal rise time and fall time (t
r
and t
f
) are specified at 15 ns or less. When the cycle time is used at
high-speed, the specification is t
r
+ t
f
≤
(T
CYC
t
EH
t
EL
).
The input signal rise time and fall time (t
r
and t
f
) are specified at 15 ns or less.
2.
3.
4.
5.
MHz.
6.
7.
8-bit parallel (6800-type) interface
; note 6; see Fig.57
T
CYC
t
AS1
t
AS2
t
AH1
t
AH2
t
DS
t
DH
t
OH
t
ACC
t
EH
t
EL
Serial interface
; note 7; see Figs 58
,
59 and 60
system cycle time
D/C, CS address set-up time
R/W address set-up time
D/C, CS address hold time
R/W address hold time
D0 to D7 data set-up time
D0 to D7 data hold time
D0 to D7 output disable time
D0 to D7 access time
E pulse width HIGH
E pulse width LOW
160
50
50
10
35
20
10
10
40
60
30
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 50 pF
T
SCYC
t
SHW
t
SLW
t
SAH
t
SAS
t
SDS
t
SDH
t
CSS
t
CSH
t
ODE1
t
ODE2
t
CEH
t
ACC
serial clock SCLK period
SCLK pulse width HIGH
SCLK pulse width LOW
D/C address hold time
D/C address setup time
SDI data set-up time
SDI data hold time
SCE to SCLK set-up time
SCE to SCLK hold time
SDO disable time
SDO disable time
SCLK to SCE hold time
SCLK to SDO access time
160
60
60
70
45
45
50
30
120
25
50
50
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
CYC(VDD1)
f
CYC(2.5)
0.44
V
DD1
×
×
=
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