2002 Aug 16
26
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
Table 12
Colour filter
CF0
C0
C1
C2
C3
C4
C5
C6
C7
to
C383
0
1
R
B
G
G
B
R
R
B
G
G
B
R
R
B
G
G
B
R
8.1
Function sets
8.1.1
NOP
The ‘no operation’ functionality is provided by the NOP
register. According to the interface protocol, first the
address 00H and then the register value 00H must be sent.
8.1.2
R
ESET
The chip has a hardware and a software reset. After
power-up, a hardware reset input (RES) must be applied.
The hardware and software resets give the same results.
After a reset the chip has the following state:
All column outputs set to V
SS
(display off)
RAM data undefined
Power-down mode
Command register set to default states (see Table 6).
8.1.3
S
OFTWARE RESET
The software reset is applied following interface protocol:
1.
Send a control byte with the software register
address (3FH).
2.
Send the register value (3FH).
8.1.4
P
OWER
-
DOWN
During Power-down (PD), all static currents are switched
off (no internal oscillator, no timing and no LCD segment
drive system) and all LCD column outputs are connected
internally to V
SS
. The I/O buffer and interface remain
operational.
When PD = 1, the PCF8832 is in the Power-down mode:
All column outputs are set to V
SS
(display off)
Interface is operational; commands can be executed
RAM contents are not cleared; RAM data can be written
Register settings remain unchanged.
8.1.5
V
ERTICAL OR HORIZONTAL ADDRESSING
When V = 0, horizontal addressing is selected and
the data is written into the DDRAM as shown in Fig.13.
When V = 1, vertical addressing is selected and the data is
written into the DDRAM as shown in Fig.14.
8.1.6
D
ISPLAY ON
/
OFF
Table 13
Display mode bits DIM and DON
DIM
DON
MODE
V
pixel
V
off(rms)
0
0
1
1
0
1
0
1
all pixels off
normal mode
all pixels on
inverse video mode
pixel value: (000) = V
off(rms)
; (111) = V
on(rms)
V
on(rms)
pixel value: (111) = V
off(rms)
; (000) = V
on(rms)