參數(shù)資料
型號: PCF8833
廠商: NXP Semiconductors N.V.
英文描述: STN RGB - 132 X 132 X 3 driver
中文描述: 超扭曲的RGB - 132 × 132 × 3驅(qū)動程序
文件頁數(shù): 66/112頁
文件大?。?/td> 469K
代理商: PCF8833
2003 Feb 14
66
Philips Semiconductors
Objective specification
STN RGB - 132
×
132
×
3 driver
PCF8833
7.3
Command decoder
The command decoder identifies command words arriving
at the interface and routes the following data bytes to their
destination. The command set is given in Chapter 6.
7.4
Grey scale controller
For a grey scale driving scheme, Frame Rate Control
(FRC) with carefully controlled mixing of the FRC pattern
on each pixel is used. The special mixing ensures that the
pattern placed on each pixel is different from each of its
neighbours. In frame rate control 16 frames form together
to produce a super-frame. All 16 frames have the same
duration.
7.5
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
7.6
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
DD1
. An external
clock signal, if used, is connected to the OSC input. In this
case the internal oscillator must be switched off by a
software command; see Section 6.2.38.
7.7
Reset
The chip has a hardware and a software reset. After
power-up a hardware reset (pin RES) must be applied.
The hardware and software reset give the same results.
After a reset, the chip has the following state; see
Section 6.2.2:
All column and row outputs are set to V
SS1
(display off)
RAM data undefined
Power-down mode
Command register set to default states; see Table 4.
7.8
LCD voltage generator and bias level generator
The LCD voltage generator and the bias level generator is
illustrated in Fig.37. The V
LCD
is generated by means of
two voltage multipliers, with voltage multiplier 1 being
programmable; see Section 6.2.39.
Behaviour of voltage multiplier 2 depends on the mode.
In the full Display mode, voltage multiplier 2 behaves as a
doubler. In the partial Display mode voltage multiplier 2
feeds the voltage of V
LCDIN1
directly to V
LCDOUT2
.
The LCD voltage generator requires in total 9 external
components (capacitors). The recommended values and
voltage ranges for the external components are specified
in Table 85. The given values should be referred to as
information only. It is recommended to check how patterns
with high load are displayed before finalizing the values.
Thebiaslevelgeneratorgeneratestherequiredbiaslevels
according to the programmed bias systems; see
Section 6.2.43.
To save power it is recommended to apply capacitors to
bias level pads (V2H, V1H, VC, V1L and V2L) of
approximately 1
μ
F. A capacitor at VC pad is expected to
be the most effective. Depending on the application of the
VC capacitor it might be advantageous or even necessary
to set the OPT bit VCBW = 1; see Table 97 and
Section 15.8.
Table 85
External components
ITEM
CAPACITOR VALUE
1 to 4.7
μ
F
1 to 4.7
μ
F
1 to 4.7
μ
F
1
μ
F
VOLTAGE RANGE
C1 to C4; C
VLCD1
C5; C
VLCD2
C
VDD2
C
VDD1
16 V
25 V
4.5 V
3.3 V
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