
2000 Dec 07
6
Philips Semiconductors
Product specification
67
×
101 Grey-scale/ECB colour dot matrix
LCD driver
PCF8820
6.2
Pad functions
6.2.1
R
OW DRIVER OUTPUTS
Rowdriveroutputs(R0 to R66)aretheoutputsfortheLCD
row drive signals. They should be connected directly to the
67 rows of the LCD. If less than 67 rows are required, the
unused outputs must be left open-circuit.
6.2.2
C
OLUMN DRIVER OUTPUTS
Column driver outputs (C0 to C100) are the outputs for the
LCD column drive signals. They should be connected
directly to the 101 columns of the LCD. If less than
101 columns are required, the unused column outputs
must be left open-circuit.
6.2.3
G
ROUND SUPPLY
The ground supply rails (V
SS1
and V
SS2
) must be
connected together. V
SS1
is related to V
DD1
and V
DD3
;
V
SS2
is related to V
DD2
.
6.2.4
S
UPPLY VOLTAGE
The supply voltage rails (V
DD1
, V
DD2
and V
DD3
) must be
connected together when the same supply is used for both
the logic circuits and for the voltage multiplier. When the
circuits are fed separately, V
DD2
and V
DD3
must be
connected to the same supply.
6.2.5
V
OLTAGE MULTIPLIER OUTPUT
V
LCDOUT
is the output of the voltage multiplier of the high
voltage generator.
6.2.6
V
OLTAGE MULTIPLIER REGULATION INPUT
V
LCDSENSE
is the regulation input of the high voltage
multiplier and must be connected to V
LCDOUT
.
6.2.7
S
UPPLY VOLTAGE OF BIAS VOLTAGE GENERATOR
V
LCD
is the supply voltage on pad V
LCDIN
for the bias
voltage generator which supplies the LCD outputs. The
voltage on pad V
LCDIN
must not be lower than V
DD1
.
If V
LCD
is generated internally, pad V
LCDOUT
must be
connected to pad V
LCDIN
.
If V
LCD
is supplied externally, the external supply voltage
must be connected to pad V
LCDIN
. An external supply
voltagemustbeappliedafterapplyingV
DD1
,anditmustbe
removed before or when removing V
DD1
(see Fig.25). It is
recommended that an external supply voltage is applied
after leaving the reset state. The external supply voltage
can stay applied in the Power-down mode.
When an external supply voltage is used, pads V
LCDIN
,
V
LCDSENSE
and V
LCDOUT
do not have to be connected
together. However, if pads V
LCDSENSE
and V
LCDOUT
are
both connected to pad V
LCDIN
, the current consumption
can be reduced under the following conditions:
The output of V
LCDOUT
is set to high-impedance
(see Table 8)
The HIGH voltage programming range is selected by
setting bit PRS = 1, the maximum voltage multiplier on
factor 8 and the V
LCD
control register on the maximum
value (see Table 2).
6.2.8
LCD
INTERMEDIATE BIAS VOLTAGES
The LCD intermediate bias voltages (V
2
, V
3
, V
4
and V
5
)
which are applied to the LCD columns and rows are
present on these pads for test purposes. They must be left
open-circuit in the application.
6.2.9
S
ERIAL DATA INPUT
SDA_IN is the serial data input from the I
2
C-bus.
6.2.10
S
ERIAL DATA OUTPUT
SDA_OUT is the serial data output (data, acknowledge)
for the I
2
C-bus. Connecting pad SDA_OUT to
pad SDA_IN makes the SDA line fully I
2
C-bus compatible.
Not connecting pad SDA_IN to pad SDA_OUT allows the
devicetobeusedinapplicationsinwhichtheacknowledge
bit is not required. In Chip-On-Glass (COG) applications, it
is sometimes beneficial not to connect pad SDA_OUT to
pad SDA_IN. This is because in COG applications where
the track resistance from pad SDA_OUT to the system
SDA line is significant, a voltage divider is created by the
bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. This divider could prevent the PCF8820 from
asserting a valid logic 0 level during an acknowledge
cycle.
In COG applications, where the acknowledge cycle is
required, the track resistance from the pad SDA_OUT to
the system SDA line must be minimized to guarantee a
valid LOW-level.
6.2.11
S
ERIAL CLOCK INPUT
SCL is the serial clock input from the I
2
C-bus.