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參數(shù)資料
| 型號： | PCF88132DA |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | (67 + 1) x 102 pixels matrix LCD driver |
| 中文描述： | （67 1）× 102像素矩陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 446K |
| 代理商： | PCF88132DA |
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2004 Mar 05
32
Philips Semiconductors
Product specification
(67 + 1)
×
102 pixels matrix LCD driver
PCF8813
11.4
Display Control
Bits D and E (see Table 8) select the display mode.
When bit MX = 0, the display RAM is written from left to
right (X = 0 is on the left side and X = 101 is on the right
side of the display). When bit MX = 1, the display RAM is
written from right to left (X = 0 is on the right side and
X = 101 is on the left side of the display).
The bit MX has an impact on the way the RAM is written.
So if horizontal mirroring of the display is required, the
RAM must first be rewritten.
When bit MY = 1, the display is mirrored vertically.
A change of bit MY has an immediate effect on the display.
When bit V = 0, horizontal addressing is selected and data
is written into the DDRAM as shown in Fig.5. When
bit V = 1, vertical addressing is selected, then data is
written into the DDRAM as shown in Fig.6.
11.5
Set Yaddress of RAM
Bits Y[3:0] define the Y address vector address of the
display RAM.
Table 11
Range of Yaddress and allowable X range
In bank 8 only three bits are accessed, and in bank 10 only
one bit is accessed.
11.6
Set X address of RAM
The X address points to the columns. The range of X is
0 to 101 (65H).
11.7
Set maximum X address or Yaddress
These two commands (X
max
[6:0] and Y
max
[3:0]) set the
maximum address for wraparound to occur for the
columns. The range of X
max
is 0 to 101. The maximum
Y address also sets the Y address for wraparound to
occur. The range of Y
max
is 0 to 8. By design, the
maximum Ysettingcannotaccessbank 10.X
max
andY
max
together also define when wraparound-to-zero takes
place. These two commands are effective only when
writing to the RAM.
11.8
Set display start line, initial start row and row 0
Set display start line L[6:0] allows the display line address
of the display RAM to be chosen. The range is from
line 0 to line 66 inclusive. The RAM address line 67 is not
available for this command as it is reserved for icons. This
command has an effect on the mapping between the data
of the RAM and the display. The L address specifies which
rows of the RAM are output to which row outputs of the
display. The value of the L address defines which row of
the RAM will be row 0. Row 0 of the display can in turn be
set by the set initial row command C[6:0].
Figure 33 shows an example of how RAM data is mapped
onto the display. In this example, the L command sets the
data on line 8 of the RAM to be displayed. This data is
displayed on a row set by the C command (16). When L
and C are set to 8 and 16 respectively, data from RAM
lines 4 to 7 is displayed on display rows 12 to 15 and RAM
data from lines 15 to 18 is displayed on display lines
23 to 26.
When MY is active (MY = 1), the data from Fig.33 is
mapped from the RAM to the display as shown in Fig.34.
Note the ‘new’ location of C after MY.
11.9
Set normal or partial display mode
When N/P = 1, the PCF8813 can operate only as a
67 + 1 row driver operating with a 1 : 68 multiplex rate.
When N/P = 0, the driver is used in free programmable
multiplex rate where up to eight different multiplex rates
can be selected in steps of 8, depending on the mask
register value M[7:0]. When the PCF8813 is operating in
FPMR mode, only the first 64 rows plus the icon row are
available to the user.
Table 12
Normal or partial mode display
YADDRESS
RAM CONTENT
ALLOWED
X RANGE
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
bank 0 (display RAM)
bank 1 (display RAM)
bank 2 (display RAM)
bank 3 (display RAM)
bank 4 (display RAM)
bank 5 (display RAM)
bank 6 (display RAM)
bank 7 (display RAM)
bank 8 (display RAM)
bank 10 (display RAM)
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
N/P
ACTION
0
1
partial mode display: 65 rows available
normal mode display: 68 rows available
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF8813U | (67 + 1) x 102 pixels matrix LCD driver |
| PCF8820 | 67 x 101 Grey-scale/ECB colour dot matrix LCD driver |
| PCF8820U | 67 x 101 Grey-scale/ECB colour dot matrix LCD driver |
| PCF8831 | STN RGB - 160 output row driver |
| PCF8831U | STN RGB - 160 output row driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8813U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:(67 + 1) x 102 pixels matrix LCD driver |
| PCF8820 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:67 x 101 Grey-scale/ECB colour dot matrix LCD driver |
| PCF8820U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:67 x 101 Grey-scale/ECB colour dot matrix LCD driver |
| PCF8831 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 160 output row driver |
| PCF8831U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:STN RGB - 160 output row driver |
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