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參數(shù)資料
| 型號： | PCF8598C-2T02 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | DRAM |
| 英文描述： | 1024 ⅴ 8-bit CMOS EEPROM with I2C-bus interface |
| 中文描述： | 1024ⅴ8位CMOS EEPROM，帶有I2C總線接口 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 395K |
| 代理商： | PCF8598C-2T02 |
Philips Semiconductors
PCF8598C-2
1024
×
8-bit CMOS EEPROM with I
2
C-bus interface
Product data
Rev. 06 — 22 October 2004
11 of 21
9397 750 14219
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. I
2
C-bus characteristics
[1]
The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
SDA input/output (pin 5)
V
IL
V
IH
V
OL
I
LO
C
i
Data retention time
t
S
LOW level input voltage
HIGH level input voltage
LOW level output voltage
output leakage current
input capacitance
0.8
0.7V
DD
-
-
-
-
-
-
-
-
0.3V
DD
+6.5
0.4
1
7
V
V
V
μ
A
pF
I
OL
= 3 mA; V
DD(min)
V
OH
= V
DD
V
I
= V
SS
data retention time
T
amb
= 55
°
C
10
years
Table 7:
V
DD
= 2.5 to 6.0 V; V
SS
= 0 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Symbol
Parameter
Characteristics
…continued
Conditions
Min
Typ
Max
Unit
Table 8:
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input voltage swing from V
SS
to V
DD
; see
Figure 9
.
Symbol
Parameter
Conditions
f
SCL
clock frequency
t
BUF
bus free time between a STOP and
START condition
t
HD;STA
START condition hold time after
which first clock pulse is generated
t
LOW
LOW level clock period
t
HIGH
HIGH level clock period
t
SU;STA
set-up time for START condition
repeated start
t
HD;DAT
data hold time
for bus compatible masters
for bus devices
t
SU;DAT
data set-up time
t
r
SDA and SCL rise time
t
f
SDA and SCL fall time
t
SU;STO
set-up time for STOP condition
I
2
C-bus characteristics
Min
0
4.7
Max
100
Unit
kHz
μ
s
4.0
μ
s
4.7
4.0
4.7
μ
s
μ
s
μ
s
5
0
250
4.0
1
300
μ
s
ns
ns
μ
s
ns
μ
s
[1]
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