參數(shù)資料
型號(hào): PCF8578T
廠商: NXP Semiconductors N.V.
元件分類: LCD驅(qū)動(dòng)器
英文描述: LCD row-column driver for dot matrix graphic displays
封裝: PCF8578HT/1<SOT357-1 (TQFP64)|<<http://www.nxp.com/packages/SOT357-1.html<1<Always Pb-free,;PCF8578T/1<SOT190-1 (VSO56)|<<http://www.nxp.com/packages/SOT190-1.html<1&l
文件頁數(shù): 9/46頁
文件大?。?/td> 274K
代理商: PCF8578T
PCF8578_6
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
17 of 46
NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
8.7 Row and column drivers
Outputs R0 to R7 and C32 to C39 are xed as row and column drivers respectively. The
remaining 24 outputs R8/C8 to R31/C31 are programmable and may be congured (in
blocks of 8) to be either row or column drivers. The row select signal is produced
sequentially at each output from R0 up to the number dened by the multiplex rate (see
Table 4). In mixed mode the remaining outputs are congured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are dened as row drivers and the outputs
C32 to C39 should be left open-circuit.
Using a 1:16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screen
congurations, i.e. a row select pulse appears simultaneously at R0 and R16/C16, R1 and
R17/C17 etc. Similarly, using a multiplex rate of 1:8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly to the LCD. Unused outputs
should be left open circuit.
Depending on the multiplex rate the following outputs are rows:
In MUX 1:8 R0 to R7
In MUX 1:16 R0 to R15/C15
In MUX 1:24 R0 to R23/C23
In MUX 1:32 R0 to R31/C31
The conguration of the outputs (row or column) and the selection of the appropriate
driver waveforms are controlled by the display mode controller.
8.8 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this
moment will be interpreted as control signals.
8.8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is dened as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH, is dened as the STOP
condition (P).
8.8.3 System conguration
A device transmitting a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message ow is the master and the devices which
are controlled by the master are the slaves.
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