參數(shù)資料
型號： PCF8578T
廠商： NXP Semiconductors N.V.
元件分類： LCD驅(qū)動器
英文描述： LCD row-column driver for dot matrix graphic displays
封裝： PCF8578HT/1<SOT357-1 (TQFP64)|<<http://www.nxp.com/packages/SOT357-1.html<1<Always Pb-free,;PCF8578T/1<SOT190-1 (VSO56)|<<http://www.nxp.com/packages/SOT190-1.html<1&l
文件頁數(shù)： 22/46頁
文件大?。?/td> 274K
代理商： PCF8578T
PCF8578_6
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 5 May 2009
29 of 46
NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
10. Static characteristics
[1]
Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor.
[2]
Resets all logic when VDD <VPOR.
[3]
Periodically sampled; not 100 % tested.
[4]
Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input (V2 to V5, VDD and VLCD)
when the specied current ows through one output under the following conditions (see Table 6 on page 11):
a) Voper =VDD V=9V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 VLCD ≥ 6.65 V; V5 VLCD ≤ 2.35 V; Iload = 150 A.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 VLCD ≥ 4.70 V; V4 VLCD ≤ 4.30 V; Iload = 100 A.
Table 17.
Static characteristics
VDD = 2.5 V to 6 V; VSS =0V; VLCD =VDD 3.5 V to VDD 9V;Tamb = 40 °C to +85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
2.5
-
6.0
V
VLCD
LCD supply voltage
VDD 9-
VDD 3.5
V
IDD
supply current
external clock;
fclk = 2 kHz
-6
15
A
internal clock;
Rext(OSC) = 330 k
-20
50
A
VPOR
power-on reset voltage
0.8
1.3
1.8
V
Logic
VIL
LOW-level input voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-VDD
V
IOL
LOW-level output current
at pins SYNC and CLK;
VOL =1V; VDD =5V
1
--mA
at pin SDA;
VOL = 0.4 V; VDD =5V
3
--mA
IOH
HIGH-level output current
at pins SYNC and CLK;
VOH =4V; VDD =5V;
--
1mA
IL
leakage current
at pins SDA, SCL, SYNC,
CLK, TEST and SA0;
Vi =VDD or VSS
1
-
+1
mA
at pin OSC;
Vi =VDD
1-
+1
A
Ci
capacitance for each I/O pin
--5
pF
LCD outputs
IL
leakage current
at pins V2 to V5;
Vi =VDD or VLCD
2-
+2
A
Voffset(DC)
DC offset voltage
on pins R0 to R7, R8/C8 to
R31/C31 and C32 to C39
-
±20
-
mV
RO
output resistance
on row output pins: R0 to
R7 and R8/C8 to R31/C31
-
1.5
3
k
on column output pins:
R8/C8 to R31/C31 and C32
to C39
-
36k
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參數(shù)描述
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