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參數(shù)資料
| 型號： | PCF8535U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 65 x 133 pixel matrix driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 1765K |
| 代理商： | PCF8535U |
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1999 Aug 24
29
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
PCF8535
7.17
I
2
C-bus interface
7.17.1
C
HARACTERISTICS OF THE
I
2
C-
BUS
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
7.17.1.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
Bit transfer is illustrated in Fig.15.
7.17.1.2
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P). The START
and STOP conditions are illustrated in Fig.16.
7.17.1.3
System configuration
The system configuration is illustrated in Fig.17.
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
7.17.1.4
Acknowledge
Each byte of 8 bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I
2
C-bus is illustrated
in Fig.18.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.15 Bit transfer.
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