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參數資料
| 型號： | PCF8535U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 65 x 133 pixel matrix driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC |
| 封裝： | DIE |
| 文件頁數： | 17/52頁 |
| 文件大小： | 1765K |
| 代理商： | PCF8535U |
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1999 Aug 24
17
Philips Semiconductors
Objective specification
65
×
133 pixel matrix driver
PCF8535
Two automated addressing modes are available; vertical
addressing (V = 1) and horizontal addressing (V = 0).
These modes change the way in which the
auto-incrementing of the address pointers is handled and
are independent of multiplex rate. The auto-incrementing
works in a way so as to aid filling of the entire RAM. It is
not a prerequisite of operation that the entire RAM is filled;
in lower multiplex modes not all of the RAM will be needed.
For these multiplex rates, use of horizontal addressing
mode (V = 0) is recommended.
Addressing the icon row is a special case as these RAM
locations are not automatically accessed. These locations
must be explicitly addressed by setting the Y address
pointer to 8.
The Y address pointer does not auto-increment when the
X address over or underflows, it stays set to 8. Writing
icon data is independent of the vertical and horizontal
addressing mode, but is effected by the mirror X bit as
described in Sections 7.15.1.2 and 7.15.1.3.
The addressing modes may be further modified by the
mirror X bit MX. This bit causes the data to be written into
the RAM from right to left instead of the normal left to right.
This effectively flips the display about the Y axis. The MX
bit affects the mode of writing into the RAM, changing the
MX bit after RAM data is written will not flip the display.
7.15.1.1
Vertical addressing: non-mirrored;
V = 1 and MX = 0
In the vertical addressing mode data is written top to
bottom and left to right. Here, the Y counter will
auto-increment from 0 to 7 and then wrap around to 0 (see
Fig.8). On each wrap over, the X counter will increment to
address the next column. When the X counter wraps over
from 127 to 0, the XM
0
bit will be set. The last address
accessible is Y = 7, X = 4 and XM
0
= 1; after this access
the counter will wrap around to Y = 0, X = 0 and XM
0
= 0.
handbook, full pagewidth
MGS675
byte number
byte order for
icon data
0
XM0 = 1
XM0 = 0
1
2
3
4
5
6
7
8
....
....
0
1
2
3
4
0
1
2
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.
.
1
1
1
1
1
1
.
1
1
Y
X address
icon data
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
0
7
6
5
4
3
2
1
0
1
1
1
1
1
1
9
8
2
2
2
2
1
1
1
1
.
2
2
2
1
2
1
1
1
1
1
1
1
1
2
2
2
2
2
Fig.8 Sequence of writing data bytes into the RAM with normal vertical addressing (V = 1 and MX = 0).
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