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參數(shù)資料
| 型號： | PCF5079T |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual-band power amplifier controller for GSM, PCN and DCS |
| 中文描述： | 雙頻功率的GSM，PCN和DCS放大器控制器 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 146K |
| 代理商： | PCF5079T |
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2001 Nov 21
8
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.5
Home position voltage
Internally, a forward voltage of an on-chip silicon diode is
provided as a default home position. This voltage matches
the requirements at the control input of most PAs and
exhibits the same temperature coefficient.
7.6
End of burst
The ramp-down should drive the PA from conduction to
shut off in a controlled way (see Fig.5). To get this result,
correctDACprogrammingisrequired,sothatthelastcode
of the DAC ramp-down (CODE
END
) is lower than the initial
code of the ramp-up (CODE
START
). In this way, the energy
corresponding to the difference between start and end
codes, applied for a certain number of Quarter-Bits (QB),
is used to balance the energy stored in the summing node
during the time interval between the start of control voltage
on pin VCD or VCG ramping-up and the feedback of a
detected ramp to the sensor input. Also a very slow
ramp-down is avoided when the PA switches off and the
loop gain becomes zero.
The amount of energy required at the end of the
ramp-down depends on the overall loop gain and on the
time needed to reach PA conduction from the home
position. At the end of a burst, when pin PU is set to
logic 0, control voltage on pin VCD or VCG is forced
to V
SS
.
handbook, full pagewidth
VSS
VVCD, VVCG
time
time (QB)
time
open
closed
open
closed
time
time
CODESTART
CODEEND
VVDAC
PU
S1, S3
S4, S5
MGT328
tA
(1)
td5
<
1
μ
s
. . . i
8
i
6
i
4
i
2
i
Fig.5 End of burst timing diagram.
(1) The exact duration of t
depends on both PCF5079 and the application loop characteristics. The contribution of PCF5079 is due mainly to the group
delay of the low-pass filter on the VDAC input (see Fig.11).
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