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參數(shù)資料
| 型號(hào)： | PCF5079T |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual-band power amplifier controller for GSM, PCN and DCS |
| 中文描述： | 雙頻功率的GSM，PCN和DCS放大器控制器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 146K |
| 代理商： | PCF5079T |
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2001 Nov 21
6
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7
FUNCTIONAL DESCRIPTION
7.1
General
The PCF5079 contains an integrated amplifier for the
detected RF voltage from the sensor, an integrator and an
active filter to build up a PA control loop for cellular
systems with a small number of passive components
suitable for dual-band applications. The active band can
be selected by means of the dedicated input BS.
The sensor amplifier can amplify signals from an
RF powerdetectorinarangeoflessthan
20 to +15 dBm.
This can comply to the PA output power range of
GSM900/1800/1900 systems when, for example, a
directional coupler with 20 dB attenuation is used for
GSM900 and a directional coupler with 18 dB attenuation
is used for GSM1800.
The external Schottky diodes for power detection (sensor)
are biased by an integrated current source of 30
μ
A.
Variations of the forward voltage with temperature have no
influence on the measured signal because they are
cancelled by the switched capacitor amplifier OP1.
An external DAC with at least 10-bit resolution (for
example, AUXDAC3 of baseband interface family
PCF5073x) is necessary to control the loop.
An integrated active filter smooths the voltage steps of the
DAC during ramp-up and ramp-down.
The operation principle is the same, independently of the
selected standard. The DAC signal and the sensor signal
are added by amplifier OP1. The voltage difference of both
signals is integrated by operational amplifier OP4
dedicated to the selected standard, which delivers the
PA control voltage on an external capacitance, CINT1 or
or CINT2, between pins VINT(N) and VCD or VCG,
respectively. The shape of the rising and falling power
burst edges can be determined by means of the DAC
voltage.
7.2
Power-up mode
The device includes a power-up input (pin PU) to switch
the IConduringtimeslotsthatareusedinTDMAsystems,
and to switch the IC off during the unused slots to reduce
current consumption.
7.3
OP4 (integrator)
The operational amplifier OP4 (integrator) consists of a
shared input stage, OP4
IN
and a dedicated output driver
for each standard, OP4
G
and OP4
D
. Depending on the
status of input BS, one driver is active and the other is kept
in power-down mode during active time slots.
7.4
Start-up and initial conditions
The PCF5079 is designed to operate in bursts, as required
in TDMA systems. Referring to Fig.4, for each time slot to
be transmitted the PCF5079 must be enabled by setting
signal PU to logic 1. Once pin PU is active, BS is taken
into account to allow correct initialisation of switches S1,
SF
D
, SF
G
, S3, S4 and S5, and of the configuration signals
PU
G
and PU
D
.
Thefeedback switchacross theunuseddriveriskeptopen
and the output voltage from the unused driver is tied to V
SS
to maintain the off state of the unused PA.
When pin PU is set to logic 1, at least 5
μ
s after V
DD
has
reacheditsfinalvalue,switches S1,theappropriateswitch
SF
D
or SF
G
and S3 are closed, and switches S4 and S5
are opened. Because switch S1 is closed, the forward
voltage of Schottky diodes D1 and D2 is sampled on
capacitors C1 and C2 respectively.
Moreover, the control voltage on pin VCD or VCG is
initially forced to be at the pre-bias voltage because the
appropriate switch SF
D
or SF
G
and S3 are closed, and S4
is opened.
After a fixed time, defined on-chip, switch S1 is opened
and the circuit is ready.
Once switch S1 is open, a ramp signal applied at
pin VDAC (at least 20
μ
s after the transition of pin PU from
logic 0 to logic 1)withanamplitudeofatleast 70 mV,from
CODE
START
to CODE
KICK
, determines the opening of
switch S3 and closing of switch S4 on the home voltage,
with a delay of 3
μ
s maximum with respect to the ramp.
After switch S3 opens (in a fixed amount of time), the
control voltage on pin VCD or pin VCG rises to the home
position to bias the PA to the beginning of the active range
of its control curve. During this time (typically 2
μ
s), the
appropriate switch SF
D
or SF
G
remains closed. When the
appropriate switch SF
D
or SF
G
is opened, switch S5 is
closed, allowing the transfer of any signal coming from
amplifier OP1. After this preset, the control voltage is free
to increase according to the control loop if the RF input is
enabled (see Fig.12).
For higher DAC ramp steps, the delay of switch S3
opening (S4 closing) is reduced while the delay between
switch SF
D
(SF
G
) opening with respect to S3 opening
(S4 closing) remains unchanged.
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