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參數資料
| 型號： | PCF5079 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual-band power amplifier controller for GSM, PCN and DCS |
| 中文描述： | 雙頻功率的GSM，PCN和DCS放大器控制器 |
| 文件頁數： | 10/28頁 |
| 文件大?。?/td> | 146K |
| 代理商： | PCF5079 |
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2001 Nov 21
10
Philips Semiconductors
Product specification
Dual-band power amplifier controller for
GSM, PCN and DCS
PCF5079
7.8
Configurations
Table 1
Operating conditions
Table 2
Band selection configuration
Note
1.
BS input has to be set before the PU transition logic 0 to logic 1.
7.9
Refer to Figs 1, 4 and 12.
Summary of current and voltage definitions
7.10
Refer to Figs 4 and 5.
Timing
POWER-UP INPUT (PU)
OPERATING MODE
0
1
disabled; reset
enabled
BAND SELECT
INPUT (BS)
(1)
BAND
DRIVER
SWITCHES
CONTROL VOLTAGE
0
GSM
OP4G
→
active;
OP4D
→
power-down
OP4D
→
active;
OP4G
→
power-down
SF
G
→
working;
SF
D
→
open
SF
D
→
working;
SF
G
→
open
V
VCG
→
working;
V
VCD
→
V
SS
V
VCD
→
working;
V
VCG
→
V
SS
1
DCS
SYMBOL
DESCRIPTION
V
VS1
V
VS2
V
VDAC
V
VCG
V
VCD
V
home
V
prebias
I
bias1
I
bias2
RF
in
RF
out
sensor signal of incident RF power or power sensor 1 signal
sensor signal of reflected RF wave or power sensor 2 signal
DAC voltage
control voltage of PA
control voltage of PA
home position voltage
prebias reference voltage; used at the start-up
bias current for detector diode D1
bias current for detector diode D2
input signal to the power amplifier
output signal from the power amplifier
SYMBOL
DEFINITION
MIN.
MAX.
UNIT
μ
s
μ
s
μ
s
μ
s
μ
s
t
d1
t
d2
t
d3
t
d4
t
d5
delay time; V
DD
application to PU input transition logic 0 to 1
delay time; PU input transition logic 0 to 1 to V
VDAC
ramp-up
V
VDAC
ramp-up detection time
delay time; ramp-up detected to V
VCD
, V
VCG
= V
home
delay time; PU input transition logic 1 to 0 to end of burst
5.0
20
3.0
2.6
1.0
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