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參數(shù)資料
| 型號： | PCF5077T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Power amplifier controller for GSM and PCN systems |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 120K |
| 代理商： | PCF5077T |
1997 Nov 19
8
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and
PCN systems
PCF5077T
Serial bus programming
A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 wires are DATA, CLK and STROBE.
The data sent to the device is loaded in bursts framed by
STROBE. Programming clock edges and their appropriate
data bits are ignored until STROBE goes active LOW.
The last four address bits are decoded on the active
STROBE edge. This produces an internal load pulse to
store the data in one of the addressed registers. To avoid
erroneous circuit operation, the STROBE pulse is not
allowed during internal data reads by the rest of the circuit.
This condition is guaranteed by respecting a minimum
STROBE pulse width after data transfer.
retained within the programming register. Additional
leading bits are ignored, and no check is made on the
number of clock pulses. The fully static CMOS design uses
virtually no current when the bus is inactive. The bus is
also programmable during power-down.
Data format
Data is entered with the most significant bit (MSB) first.
The leading 10 bits p15 to p6 are the data field, the
following bits p5 and p4 form the subaddress, while the
last 4 bits p3 to p0 are the device address field.
The PCF5077T uses only one of the available addresses.
The format is given in Table 2.
The correspondence between data and address fields is
given in Table 3 and the description in Table 4.
All three registers in Table 3 are set to 00H during reset.
Table 2
Programming register format
Table 3
Register bit allocation
Table 4
Description of bits used in Table 3
DATA BITS
SUBADDRESS
DEVICE ADDRESS
MSB
LSB
p15
data9
p14 to p8
data8 to data2
p7
p6
p5
p4
p3
p2
p1
p0
data1
data0
Sadd1
Sadd0
add3
add2
add1
add0
DATA FIELD (D9 TO D0)
SUBADDRESS
DEVICE ADDRESS
MSB
LSB
p15
Vk5
Vh5
PL7
p14
Vk4
Vh4
PL6
p13
Vk3
Vh3
PL5
p12
Vk2
Vh2
PL4
p11
Vk1
Vh1
PL3
p10
Vk0
Vh0
PL2
p9
Lim1
DVh1 DVh0
PL1
p8
Lim0
p7
DC
DR1
DF1
p6
Test
DR0
DF0
p5
0
0
1
p4
0
1
1
p3
1
1
1
p2
0
0
0
p1
1
1
1
p0
0
0
0
PL0
BITS
DESCRIPTION
Vk5 to Vk0
Vh5 to Vh0
PL7 to PL0
Lim1 and Lim0
DC
Test
DVh1 and DVh0
DR1
DR0
DF1
DF0
6 bits to control the kick voltage in 64 steps
6 bits to control the home position voltage in 64 steps
8 bits to control the power level in 256 steps
2 bits to control the limiter voltage (see Table 5)
direct control with ramping function (control loop is switched off when DC = 1)
test mode (Test = 1);
must always be set to logic 0 in application
2 bits to set the temperature coefficient of V
HOME
(see Table 6)
gain factor of OP1
gain factor for slope generator output
enable of the 3-state output on pin DF (for DF1 = 0, pin DF is in 3-state mode)
data output on pin DF
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