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參數(shù)資料
| 型號： | PCF5077T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Power amplifier controller for GSM and PCN systems |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 120K |
| 代理商： | PCF5077T |
1997 Nov 19
4
Philips Semiconductors
Preliminary specification
Power amplifier controller for GSM and
PCN systems
PCF5077T
PINNING
SYMBOL
PIN
DESCRIPTION
VS
DF
V
DDA1
BVS
TRIG
V
DDD
PD
CLK13
1
2
3
4
5
6
7
8
sensor signal input
programmable 3-state output
analog supply voltage 1
buffered sensor signal output
trigger signal input
digital supply voltage
power-down input (active LOW)
13 MHz master clock input
(low-swing)
serial bus strobe signal input
serial bus clock signal input
serial bus data signal input
digital ground
analog ground
integrator output
integrator inverting input
analog supply voltage 2 (for OP4)
STROBE
CLK
DATA
V
SSD
V
SSA
V
INT(O)
V
INT(N)
V
DDA2
9
10
11
12
13
14
15
16
Fig.2 Pin configuration.
handbook, halfpage
PCF5077T
MGK909
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VS
DF
VDDA1
BVS
TRIG
VDDD
PD
CLK13
STROBE
CLK
DATA
VSSD
VSSA
VINT(O)
VINT(N)
VDDA2
FUNCTIONAL DESCRIPTION
General
This CMOS device integrates operational amplifiers, two
digital-to-analog converters and a serial bus interface to
implement an ‘Integrating-Controller’ (see Fig.1). It is
designed to control both the power level and the up- and
down-ramping of GSM/PCN transmit bursts.
The GSM/PCN power-up and power-down ramping curves
are generated on-chip, using an internal clock frequency of
f
clk
2.166 MHz
, that is generated internally by
dividing the external 13 MHz clock signal by six.
Generally, the power amplifier is ramped-up after a rising
edge on pin TRIG and ramped-down after a falling edge.
The content of the power level register (bits PL7 to PL0)
determines which of the 2
×
256 possible values the top of
the burst will have.
To match the controller to different power modules and
sensors several parameters must be adapted.
The following parameters influence the performance of the
transmission system:
The external capacitor C1 in Fig.1 determines the
maximum bandwidth of the power control loop,
T
cy
--1
=
depending on the highest steepness of the control curve
of the power module and on the sensor attenuation.
The maximum output voltage at pin V
INT(O)
to protect the
power module: the limiting value of V
INT(O)
can be set to
4, 3.3 or 2.55 V, depending on the contents of the limiter
register (bits Lim1 and Lim0). This limiting results in a
ringing at V
INT(O)
(typ. 200 mV peak-to-peak value) but it
will not be transferred to the antenna because the power
module is in saturation. The limiter register bits Lim1
and Lim0 can be used to switch off the limiter option
(see Table 5).
The home position at V
INT(O)
: the integrator output
voltage at home position (PD = HIGH and TRIG = LOW)
is programmed by means of the V
HOME
register.
Bits Vh5 to Vh0 are fed into a 6-bit DAC that generates
a part of V
HOME
.
The temperature behaviour of the home position:
bits DVh1 and DVh0 can be used to compensate
temperature dependencies (
2 or
4 mV/K) of the
control curves of the power module. This completes the
setting of V
HOME
.
The KICK voltage: the 6 bits of the V
KICK
register
(Vk5 to Vk0) determine the differential integrator input
voltage just after a ramp-up starting signal is detected.
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