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參數(shù)資料
| 型號： | PCF2105 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LCD controller/driver |
| 中文描述： | LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 289K |
| 代理商： | PCF2105 |
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1998 Jul 30
22
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
11 INTERFACE TO MICROCONTROLLER (I
2
C-BUS
INTERFACE)
11.1
Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, 2-line communication
between different ICs or modules. The 2 lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
11.2
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH-level period of the clock pulse as changes in the
data line at this time will be interpreted as a control signal
(see Fig.16).
11.3
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.17).
11.4
System configuration
A device generating a message is a transmitter, a device
receiving a message is the receiver. The device that
controls the message is the master and the devices which
are controlled by the master are the slaves (see Fig.18).
11.5
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of 8 bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH signal put
on the bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition (see Fig.19).
11.6
I
2
C-bus protocol
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I
2
C-bus configuration for the different
PCF2105 read and write cycles is illustrated in
Figs 20, 21 and 22.
Fig.16 Bit transfer.
handbook, full pagewidth
MBC621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
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