1
1
P
P
L
P
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Table 3
Instructions (note 1)
Notes
1.
In the I
2
C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I
2
C-bus mode a control byte is required when bit RS or R/W is changed;
control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.
2.
Example: f
osc
= 150 kHz,
; 3 cycles = 20
μ
s; 165 cycles = 1.1 ms.
INSTRUCTION
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
(2)
NOP
Clear display
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
no operation
clears entire display and sets DDRAM
address 00 in Address Counter (AC)
sets DDRAM address 00 in the AC;
also returns shifted display to original
position; DDRAM contents remain
unchanged
sets cursor move direction and specifies
shift of display; these operations are
performed during data write and read
sets entire display on/off (D), cursor
on/off (C) and blink of cursor position
character (B)
moves cursor and shifts display without
changing DDRAM contents
sets interface data length (DL), number
of display lines (N, M) and voltage
generator control (G); bit G is not used
sets CGRAM address
0
165
Return home
0
0
0
0
0
0
0
0
1
0
3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift
0
0
0
0
0
1
S/C
R/L
0
0
3
Function set
0
0
0
0
1
DL
N
M
G
0
3
Set CGRAM
address
Set DDRAM
address
Read busy flag and
address
Read data
Write data
0
0
0
1
A
CG
3
0
0
1
A
DD
sets DDRAM address
3
0
1
BF
A
C
reads BF indicating internal operation is
being performed and reads AC contents
reads data from CGRAM or DDRAM
writes data to CGRAM or DDRAM
0
1
1
1
0
read data
write data
3
3
T
cy
f
osc
-1
6.67
μ
s
=
=