1998 May 11
6
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
Table 1
Pin functions; note 1
Note
1.
When the I
2
C-bus is used, the parallel interface pin E must be defined as E = 0. In I
2
C-bus read mode DB7 to DB0
should be connected to V
DD
or left open-circuit.
a) When the parallel bus is used, pins SCL and SDA must be connected to V
SS
or V
DD
; they may not be left
unconnected.
b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB3 can either be set to V
SS
or V
DD
instead of leaving them open.
NAME
FUNCTION
DESCRIPTION
RS
register select
RS selects the register to be accessed for read and write; there is an internal pull-up
on this pin
RS = 0 selects the instruction register for write and the busy flag and address
counter for read
RS = 1 selects the data register for both read and write
R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an
internal pull-up on this pin
pin E is set HIGH to signal the start of a read or write operation; data is clocked in or
out of the chip on the negative edge of the clock
the bi-directional, 3-state data bus transfers data between the system controller and
the PCF2103; DB7 may be used as the busy flag, signalling that internal operations
are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are
used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the
data lines
these pins output the data for columns
R/W
read/write
E
data bus clock
DB7 to DB0
data bus
C1 to C60
column driver
outputs
row driver
outputs
LCD power
supply
oscillator
R1 to R18
these pins output the row select waveforms to the display; R17 and R18 drive the
icons
positive power supply for the liquid crystal display
V
LCD
OSC
when the on-chip oscillator is used this pin must be connected to V
DD
; an external
clock signal, if used, is input at this pin
input for the I
2
C-bus clock signal
I/O for the I
2
C-bus data line
the hardware sub-address line is used to program the device sub-address for two
different PCF2103s on the same I
2
C-bus
must be connected to V
SS
; not user accessible
power-down pad PD selects chip power-down mode; for normal operation PD = 0
SCL
SDA
SA0
serial clock line
serial data line
address pin
T1
PD
test pad