參數(shù)資料
型號(hào): PCF2103EU
廠商: NXP Semiconductors N.V.
英文描述: LCD controllers/drivers
中文描述: LCD控制器/驅(qū)動(dòng)器
文件頁(yè)數(shù): 35/56頁(yè)
文件大?。?/td> 300K
代理商: PCF2103EU
1998 May 11
35
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
13 AC CHARACTERISTICS
V
DD
= 1.8 to 5.5 V; V
SS
= 0 V; V
LCD
= 2.2
6.5 V; T
amb
=
40 to +85
°
C; unless otherwise specified.
Note
1.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
V
IL
and V
IH
with an input voltage swing of V
SS
to V
DD
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
fr(LCD)
f
osc
f
osc(ext)
t
OSCST
LCD frame frequency (internal clock)
oscillator frequency (not available at any pin)
external clock frequency
oscillator start-up time after PD going from
logic 1 to logic 0
V
DD
= 5.0 V
45
140
140
81
250
200
147
450
450
300
Hz
kHz
kHz
μ
s
Bus timing characteristics: parallel interface;
note 1
W
RITE OPERATION
(
WRITING DATA FROM MICROCONTROLLER TO
PCF2103); see Fig.23
T
en(cy)
t
W(en)
t
su(A)
t
h(A)
t
su(D)
t
h(D)
R
EAD OPERATION
(
READING DATA FROM
PCF2103
TO MICROCONTROLLER
); see Fig.24
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
220
50
25
60
25
ns
ns
ns
ns
ns
ns
T
en(cy)
t
W(en)
t
su(A)
t
h(A)
t
d(D)
t
h(D)
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
data hold time
500
220
50
25
20
150
100
ns
ns
ns
ns
ns
ns
Timing characteristics: I
2
C-bus interface;
note 1
f
SCL
t
LOW
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
f
C
B
t
SU;STA
t
HD;STA
t
SU;STO
t
SW
SCL clock frequency
SCL clock LOW period
SCL clock HIGH period
data set-up time
data hold time
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
set-up time for a repeated START condition
START condition hold time
set-up time for STOP condition
tolerable spike width on bus
1.3
0.6
100
0
0.6
0.6
0.6
400
300
300
400
50
kHz
μ
s
μ
s
ns
ns
ns
ns
pF
μ
s
μ
s
μ
s
ns
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