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參數(shù)資料
| 型號： | PCF2103 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LCD controllers/drivers |
| 中文描述： | LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 23/56頁 |
| 文件大?。?/td> | 300K |
| 代理商： | PCF2103 |
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1998 May 11
23
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
8.4
Display control (and partial power-down mode)
8.4.1
D
The display is on when D = 1 and off when D = 0. Display
data in the DDRAM are not affected and can be displayed
immediately by setting D to logic 1.
When the display is off (D = 0) the chip is in partial
power-down mode:
The LCD outputs are connected to V
SS
Bias generator is turned off.
3 oscillator cycles are required after sending the
‘display off’ instruction to ensure all outputs are at V
SS
,
afterwards OSC can be stopped. If the oscillator is running
during partial power-down mode (‘display off’) the chip can
still execute instructions. Even lower current consumption
is obtained by inhibiting the oscillator (OSC = V
SS
).
To ensure I
DD
< 2
μ
A the parallel bus pins DB7 to DB0
should be connected to V
DD
; RS and R/W to V
DD
or left
open-circuit and PD to V
DD
. Recovery from power-down
mode: put PD back to logic 0, if necessary put OSC back
to V
DD
and send a ‘display control’ instruction with D = 1 to
enable the display again.
8.4.2
C
The cursor is displayed when C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions
I/D, etc. remain in operation during display data write.
The cursor is displayed using 5 dots in the 8th line (see
Fig.5).
8.4.3
B
The character indicated by the cursor blinks when B = 1.
The cursor character blink is displayed by switching
between display characters and all dots on with a period of
approximately 1 s, with
The cursor underline and the cursor character blink can be
set to display simultaneously.
8.5
Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line. When the displayed data is shifted
repeatedly all lines shift at the same time; displayed
characters do not shift into the next line.
f
BLINK
f
52224
----------------
=
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
8.6
Function set
8.6.1
DL (
PARALLEL MODE ONLY
)
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)
when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit
application DB3 to DB0 should be left open-circuit (internal
pull-ups). Hence in the first ‘function set’ instruction after
power-on N and H are set to logic 1. A second
‘function set’ must then be sent (2 nibbles) to set N and H
to their required values.
‘Function set’ from the I
2
C-bus interface sets the DL bit to
logic 1.
8.6.2
M
Chooses either 1-line by 24 display (M = 0) or 2-line by
12 display (M = 1).
8.6.3
H
When H = 0 the chip can be programmed via the standard
11 instruction codes used in the PCF2116 and other LCD
controllers.
When H = 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
8.7
Set CGRAM address
‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM
address A
CG
into the address counter (binary A[5] to A[0]).
Data can then be written to or read from the CGRAM.
Attention:
the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A[6] to A[0]). With the ‘set CGRAM address’
command, only bits 5 down to 0 are set. Bit 6 can be set
using the ‘set DDRAM address’ command first, or by using
the auto-increment feature during CGRAM write.
All bits 6 to 0 can be read using the
‘read busy flag and address counter’ command.
When writing to the lower part of the CGRAM, ensure that
bit 6 of the address is not set (e.g. by an earlier DDRAM
write or read action).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF2103EU | LCD controllers/drivers |
| PCF2104L | LCD controller/driver |
| PCF2104LU | LCD controller/driver |
| PCF2104N | LCD controller/driver |
| PCF2104NU | LCD controller/driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF2103EU | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controllers/drivers |
| PCF2103EU/2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF2103EU/2/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controllers/drivers |
| PCF2103EU/F2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF2103FAMILY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
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