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參數(shù)資料
| 型號： | PCD8544U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 48 x 84 pixels matrix LCD controller/driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC168 |
| 封裝： | BUMP, DIE-168 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 154K |
| 代理商： | PCD8544U |
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1999 Apr 12
15
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD controller/driver
PCD8544
8.1
Initialization
Immediately following power-on, the contents of all internal
registers and of the RAM are undefined.
A RES pulse
must be applied
. Attention should be paid to the
possibility that the
device may be damaged
if not properly
reset.
All internal registers are reset by applying an external RES
pulse (active LOW) at pad 31, within the specified time.
However, the RAM contents are still undefined. The state
after reset is described in Section 8.2.
TheRES input must be
≤
0.3V
DD
when V
DD
reaches V
DDmin
(or higher) within a maximum time of 100 ms after V
DD
goes HIGH (see Fig.16).
8.2
Reset function
After reset, the LCD driver has the following state:
Power-down mode (bit PD = 1)
Horizontal addressing (bit V = 0) normal instruction set
(bit H = 0)
Display blank (bit E = D = 0)
Address counter X
6
to X
0
= 0; Y
2
to Y
0
= 0
Temperature control mode (TC
1
TC
0
= 0)
Bias system (BS
2
to BS
0
= 0)
V
LCD
is equal to 0, the HV generator is switched off
(V
OP6
to V
OP0
= 0)
After power-on, the RAM contents are undefined.
8.3
Function set
8.3.1
B
IT
PD
All LCD outputs at V
SS
(display off)
Bias generator and V
LCD
generator off, V
LCD
can be
disconnected
Oscillator off (external clock possible)
Serial bus, command, etc. function
Before entering Power-down mode, the RAM needs to
be filled with ‘0’s to ensure the specified current
consumption.
8.3.2
B
IT
V
When V = 0, the horizontal addressing is selected.
The data is written into the DDRAM as shown in Fig.6.
When V = 1, the vertical addressing is selected. The data
is written into the DDRAM, as shown in Fig.5.
8.3.3
B
IT
H
When H = 0 the commands ‘display control’, ‘set
Y address’ and ‘set X address’ can be performed; when
H = 1, the others can be executed. The ‘write data’ and
‘function set’ commands can be executed in both cases.
8.4
Display control
8.4.1
B
ITS
D
AND
E
Bits D and E select the display mode (see Table 2).
8.5
Set Y address of RAM
Y
n
defines the Y vector addressing of the display RAM.
Table 3
Y vector addressing
8.6
Set X address of RAM
The X address points to the columns. The range of X is
0 to 83 (53H).
8.7
Temperature control
The temperature coefficient of V
LCD
is selected by bits
TC
1
and TC
0
.
8.8
Bias value
The bias voltage levels are set in the ratio of
R - R - nR - R - R, giving a 1/(n + 4) bias system. Different
multiplex rates require different factors n (see Table 4).
This is programmed by BS
2
to BS
0
. For Mux 1 : 48, the
optimum bias value n, resulting in 1/8 bias, is given by:
(1)
Y
2
0
0
0
0
1
1
Y
1
0
0
1
1
0
0
Y
0
0
1
0
1
0
1
BANK
0
1
2
3
4
5
n
48
3
–
3.928
4
=
=
=
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