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參數(shù)資料
| 型號： | PCD8544U |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 48 x 84 pixels matrix LCD controller/driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC168 |
| 封裝： | BUMP, DIE-168 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 154K |
| 代理商： | PCD8544U |
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1999 Apr 12
11
Philips Semiconductors
Product specification
48
×
84 pixels matrix LCD controller/driver
PCD8544
8
INSTRUCTIONS
The instruction format is divided into two modes: If D/C
(mode select) is set LOW, the current byte is interpreted as
command byte (see Table 1). Figure 8 shows an example
of a serial data stream for initializing the chip. If D/C is set
HIGH, the following bytes are stored in the display data
RAM. After every data byte, the address counter is
incremented automatically.
The level of the D/C signal is read during the last bit of data
byte.
Each instruction can be sent in any order to the PCD8544.
The MSB of a byte is transmitted first. Figure 9 shows one
possible command stream, used to set up the LCD driver.
The serial interface is initialized when SCE is HIGH. In this
state, SCLK clock pulses have no effect and no power is
consumed by the serial interface. A negative edge on SCE
enables the serial interface and indicates the start of a data
transmission.
Fig.8 General format of data stream.
handbook, halfpage
MGL666
data
data
LSB (DB0)
Fig.9 Serial data stream, example.
handbook, full pagewidth
MGL642
function set (H = 1)
bias system
set VOP
temperature control
function set (H = 0)
display control
X address
Y address
Figures 10 and 11 show the serial bus protocol.
When SCE is HIGH, SCLK clock signals are ignored;
during the HIGH time of SCE, the serial interface is
initialized (see Fig.12)
SDIN is sampled at the positive edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1); it is read with the eighth SCLK
pulse
If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects bit 7 of the next byte at
the next positive edge of SCLK (see Fig.12)
A reset pulse with RES interrupts the transmission.
No data is written into the RAM. The registers are
cleared. If SCE is LOW after the positive edge of RES,
the serial interface is ready to receive bit 7 of a
command/data byte (see Fig.13).
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相關代理商/技術參數(shù) |
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|---|---|
| PCD8572 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Microchip Technology Inc 功能描述: |
| PCD8572/J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| PCD8572/P | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Microchip Technology Inc 功能描述: |
| PCD8572/P010 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Microchip Technology Inc 功能描述: |
| PCD8572I | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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