參數(shù)資料
型號： PCD6003H
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡
英文描述： Digital telephone answering machine chip
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 20/96頁
文件大小： 385K
代理商： PCD6003H
2001 Apr 17
20
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
10 THE MICROCONTROLLER
The embedded MS80C51 microcontroller controls the
Digital Telephone Answering Machine (DTAM) chip by
means of Special Function Registers (SFRs). SFRs are
defined for the blocks MCB, TICB, PCON, DSP, I
2
C-bus,
ports P1, P3 and P4, MA, MSK and ANA (the analog
blocks). All of these (except SFR PCON) are shown in the
block diagram in Fig.1. The architecture of the
microcontroller itself and the interface to these blocks are
described in this chapter.
10.1
Microcontroller architecture
The microcontroller architecture and its environment is
shown in Fig.7.
The microcontroller has some application-specific
peripherals such as the I
2
C-bus, Watchdog Timer (WD),
P1, P3, P4,MCB,ExternalInterfacewithMA port,SFRsof
the DSP block, the TICB and the ANA block. Most of these
functions and SFRs are located in the Application Specific
Function block (ASF), see Fig.7.
The 80C51 core contains the 80C51 standard functions
such as Timer 0 and Timer 1, power-down/idle states and
a 15 vector dual-level interrupt controller INT15L2.
Furthermore, the microcontroller contains the Metalink
enhanced hooks protocol which enables Metalink
emulation via ALE, PSEN, EA, P0 and P2. The external
programmemoryaccessisdoneviathestandardPorts P0
and P2. Connection of external flash memory is done via
the P4, P0 and P2 I/O pads. The microcontroller Clock
Driver (CD) has no clock divider, which means that the
microcontroller operates on 6 microcontroller_CLK clocks
per machine cycle.
The 80C51 has a few basic modes of operation: Reset,
Normal, Metalink, Test (various) Idle and Power-down.
Entering the Metalink mode can be done via inputs ALE
and EA during a reset.
The Idle mode can be entered by setting the IDL bit in the
PCON register. Leaving the Idle mode can be done via a
master reset (RSTIN), any external interrupt, a
DSP_event, TIME_event or RTC_event, Timer 0 and
Timer 1, I
2
C-bus interrupt, MSK_event or FS_event; if
these interrupts are enabled.
The Power-down mode can be entered by setting the
PD bit in PCON. The power-down logic of the
microcontroller will turn all microcontroller clocks off.
The TIME_event, DSP_event, RTC_event and
EX2 to EX6 are mixed with EX0 (see Fig.10) and therefore
make use of the standard wake-up circuitry of the 80C51.
These interrupts should be active for more than 6 clocks
(read, modify, write of IRQ1 takes 1 instruction) to
guarantee the interrupt for the microcontroller.
Setting the PD bit of PCON after setting the system-off bit
of SPCON, will trigger the analog section to turn off the
oscillator and therefore the whole chip. In order to keep
staticsupplycurrentsminimal,itisadvisedtoswitchoffthe
digital-to-analog part of the CODECs before going in this
system-off mode. Wake-up from system-off can be done
viaaRSTINoranexternalinterruptEX0 to EX6(iftheEX0
interrupt is enabled) or EX1 (if the EX1 interrupt is
enabled). A wake-up from system-off will always reset the
PCD6003. The EX interrupt condition should last more
than 4096 + 64 + 4 clocks to be sure that the interrupt is
handled when entering the normal mode. If the interrupt is
shorter the microcontroller will only enter the normal mode
after the reset is gone.
10.2
Memory mapping
The memory map of the 80C51 is shown in Fig.8.
In addition to all the SFRs, the microcontroller has
128 bytes of directly addressable (DATA) memory,
128 bytes of indirectly addressable (IDATA) memory and
512 bytes of AUX RAM, the on-chip ‘MOVX’ addressable
(XDATA) memory. On-chip XDATA memory access can
be disabled by setting the ARD bit in PCON to logic 1. The
internal32-kbyteROMofmicrocontrollerprogram(CODE)
memory can be accessed when EA is set to logic 1.
Via Ports P0, MA, P2 and P4 it is possible to access up to
512 kbytes of external speech data memory stored in a
parallel flash memory. A CAD flash memory can also be
mappedinthisarea.Aserial(SPIorMicrowirecompatible)
flash memory can be connected to P4 which is controlled
by the MCB. Up to 64 kbytes of program (CODE) memory
can be connected to the P0, P2 and PSEN pads. This can
be any external program memory (like the MON51 target
debug ROM) if EA is logic 0.
When the EAM SFR bit (P4CFG.5) is logic 0 (default after
reset), the XRAM-mapped control registers can only be
accessed if P4.3 is logic 1. Otherwise, XRAM addressing
is independent of the value of the P4.3 SFR bit.
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