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參數(shù)資料
| 型號： | PCD5043H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DECT burst mode controller |
| 中文描述： | TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP64 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 109K |
| 代理商： | PCD5043H |
1996 Oct 31
9
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5043
Fig.3 Internal clocking scheme of the PCD5043.
handbook, full pagewidth
MBH708
480
bit counter
3.456 MHz system
clock for ADPCM codec
24
slot counter
100 Hz
frame sync
1152 kHz
system/bit clock
clock corrections in this level
unless disabled PCD5041's mode register
COMPARATOR
'SYNC' event
FSx signals
(8 kHz)
16
slot counter
2
144
3
4 (
±
1)
13.824 MHz system clock
6.912 MHz system clock
6.4
Speech interface
The speech interface block performs the following
functions:
Connection to a 1152 kbits/s interface in a handset and
a simple base station in the so called ‘12 slot mode’
Connection to a n x 64 kbits/s interface in base stations
in the so called ‘32 slot mode’
Autonomous storing/fetching of ADPCM speech data
in/from the PCD5043’s common data memory, using
internal addressing logic
Muting of speech data
Local call.
6.4.1
12-
SLOT MODE
The 12-slot mode is selected if up to 4 ADPCM codecs are
connected to the PCD5043, where the PCD5043 is the
master of these codecs. In a handset, or in a simple base
stations which is connected with up to 4 analog lines to the
public network, the PCD5043 is master of the codecs.
Each codec is connected with a separate framing
reference signal (FS1 to FS4) to the PCD5043. In the
QFP64 package, 2 framing signals FS1 and FS2 are
available, whereas in the LQFP80 package 4 framing
signals can be used (FS1 to FS4). When more codecs are
to be connected, the FS5 to FS12 signals have to be
generated externally. When using the framing signals
FS1 to FS4, no interface logic is required when using the
PCD5032 ADPCM codec.
A speech-slot control table is used to determine where to
store/fetch speech data for transmission and reception.
The hardware speech-interface is capable of addressing
the right speech buffer for the relevant speech slot, and will
maintain a counter carrying the offset to the correct
stored/fetched address.
6.4.2
32-
SLOT MODE
The 32-slot mode is used to connect the PCD5043 to a
digital interface with a data rate of n
×
64 kbits/s; where
n = 1 to 32 is the number of speech slots. This equates to
data rates from 64 kbits/s to 2048 kbits/s.
Up to 12 of the 32 speech slots can be used
simultaneously. The same kind of speech-slot control table
used in the 12-slot mode is used for the 32-slot mode.
6.4.3
M
UTING
Due to various reasons the quality of the incoming speech
data may be degraded significantly. By muting the speech
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