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參數(shù)資料
| 型號： | PCD5043H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DECT burst mode controller |
| 中文描述： | TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP64 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 109K |
| 代理商： | PCD5043H |
1996 Oct 31
4
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5043
4
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MBH742
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
DATA MEMORY
2 kbyte RAM
TIMING, CONTROL,
CLOCK
GENERATION
PCC
PROGRAM MEMORY
4 kbyte ROM
MICROCONTROLLER
INTERFACE
SPEECH
INTERFACE
internal
bus
PCD5043
DECT
BURST MODE
CONTROLLER
to CODEC/
Highway
3-wire synthesizer
interface
Rx/Tx data
8051/68000
interface
5
PINNING
(see Fig.2)
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
AD0 to AD7
ALE
CS
A8 to A10
V
DD1
PROC_CLK
1 to 8
9
10
13 to 11
14
15
I/O
I
I
I
P
O
address/Data bus
address latch enable
chip select (active LOW)
address bus
positive supply 1
microcontroller clock; programmable from f
CLK
/64 to f
CLK
, where f
CLK
is the crystal oscillator frequency
negative supply 1
crystal oscillator input
crystal oscillator output
negative supply
watchdog timer output; intended to reset the external microcontroller
when expired
read (active LOW)
write (active LOW)
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
interrupt (active LOW)
100 Hz frame timer
V
SS1
XTAL1
XTAL2
V
SS2
RESET_OUT
16
17
18
19
20
P
I
O
P
O
RD
WR
RDY
21
22
23
I
I
O
INT
CLK100
24
25
O
O
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