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參數(shù)資料
| 型號： | PCD5043H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DECT burst mode controller |
| 中文描述： | TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP64 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 109K |
| 代理商： | PCD5043H |
1996 Oct 31
5
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5043
V
SS3
DO
FS1
26
27
28
P
O
I/O
negative supply 3
3-state data output on the speech interface
8 kHz framing signal to ADPCM CODEC 1 output, for simple base +
handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 2 in the base station mode
data input on the speech interface
simple base + handset; 1152 kHz data clock (output), otherwise
2048 kHz data clock (input) signal
3.456 MHz clock (nominal value, used to adjust system timing)
selects one of two antennas
Transmitter Enable (active LOW)
Transmitter Power Ramp control
serial 8-bit data can be read in for each slot; REMote radio
lock indication from synthesizer
negative supply 4
reference frequency for the synthesizer, i.e. the crystal oscillator
clock f
CLK
positive supply 2
synthesizer enable
clock signal, to be used with S_DATA
serial data to the synthesizer
synthesizer power-down control
VCO bandswitch control signal
control signal for dual synthesizer schemes
serial output data to transmitter
switches off the crystal oscillator, and prevents all RF signals from
becoming active
selects various test modes.; normal operation set to 0
analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
selects various test modes; normal operation set to 0
selects various test modes; normal operation set to 0
receive data
receiver enable (active LOW)
receiver power-down
slice time constant control
positive supply 3
negative supply 5
reference input for the A/D converter
power supply for data RAM
in the base station the signal is the SYNCPORT
FS2
DI
DCK
29
30
31
O
I
O
CLK3
ANT_SW
T_ENABLE
T_POWER_RMP
RMT_STAT
SYNTH_LOCK
V
SS4
REF_CLK
32
33
34
35
36
37
38
39
O
O
O
O
I
I
P
O
V
DD2
S_ENABLE
S_CLK
S_DATA
S_POWER_DWN
VCO_BND_SW
1200 HZ
T_DATA
SET_OFF_IN
40
41
42
43
44
45
46
47
48
P
O
O
O
O
O
O
O
I
TEST1
RSSI_AN
49
50
I
I
TEST2
TEST3
R_DATA
R_ENABLE
R_POWER_DWN
SLICE_CTR
V
DD3
V
SS5
V
REF
V
DD(RAM)
SYNCPORT
51
52
53
54
55
56
57
58
59
60
61
I
I
I
O
O
O
P
P
I
P
I/O
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
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