參數(shù)資料
型號： PCD5041HZ
廠商： NXP SEMICONDUCTORS
元件分類： 無繩電話/電話
英文描述： DECT burst mode controller
中文描述： TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP80
文件頁數(shù)： 5/28頁
文件大?。?/td> 134K
代理商： PCD5041HZ
1996 Oct 31
5
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
INT
CLK100
V
SS3
DO
FS3
24
25
26
27
27
29
31
32
33
O
O
P
O
I/O
interrupt (active LOW)
100 Hz frame timer
negative supply 3
3-state data output on the speech interface
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 1 output, for simple
base + handset, otherwise 8 kHz framing input
8 kHz framing signal to ADPCM CODEC 2 in the base station
mode
data input on the speech interface
simple base + handset; 1152 kHz data clock (output),
otherwise 2048 kHz data clock (input) signal
3.456 MHz clock (nominal value, used to adjust system
timing)
selects one of two antennas
Transmitter Enable (active LOW)
Transmitter Power Ramp control
serial 8-bit data can be read in for each slot; REMote radio
lock indication from synthesizer
negative supply 4
reference frequency for the synthesizer, i.e. the crystal
oscillator clock f
CLK
positive supply 2
synthesizer enable
clock signal, to be used with S_DATA
serial data to the synthesizer
synthesizer power-down control
VCO bandswitch control signal
control signal for dual synthesizer schemes
serial output data to transmitter
switches off the crystal oscillator, and prevents all RF signals
from becoming active
selects various test modes.; normal operation set to 0
analog signal (for basic DECT systems), peak signal strength
measured after a lowpass filter
selects various test modes; normal operation set to 0
selects various test modes; normal operation set to 0
receive data
FS1
28
34
I/O
FS4
35
I/O
FS2
29
36
O
DI
DCK
30
31
37
38
I
O
CLK3
32
39
O
ANT_SW
T_ENABLE
T_POWER_RMP
RMT_STAT
SYNTH_LOCK
V
SS4
REF_CLK
33
34
35
36
37
38
39
40
41
43
44
45
46
47
O
O
O
I
I
P
O
V
DD2
S_ENABLE
S_CLK
S_DATA
S_POWER_DWN
VCO_BND_SW
1200 HZ
T_DATA
SET_OFF_IN
40
41
42
43
44
45
46
47
48
48
49
51
52
53
54
55
56
57
P
O
O
O
O
O
O
O
I
TEST1
RSSI_AN
49
50
58
60
I
I
TEST2
TEST3
R_DATA
51
52
53
I
I
I
61
63
SYMBOL
PIN
TYPE
(2)
DESCRIPTION
QFP64
LQFP80
(1)
相關(guān)PDF資料
PDF描述
PCD5042H DECT burst mode controller
PCD5042HZ DECT burst mode controller
PCD5042 DECT burst mode controller
PCD5043 DECT burst mode controller
PCD5043H DECT burst mode controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCD5042 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller
PCD5042H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller
PCD5042HZ 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller
PCD5043 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller
PCD5043H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT burst mode controller
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