參數(shù)資料
型號(hào): PCD5041HZ
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 無(wú)繩電話(huà)/電話(huà)
英文描述: DECT burst mode controller
中文描述: TELECOM, CORDLESS, BURST MODE CONTROLLER, PQFP80
文件頁(yè)數(shù): 11/28頁(yè)
文件大小: 134K
代理商: PCD5041HZ
1996 Oct 31
11
Philips Semiconductors
Objective specification
DECT burst mode controller
PCD5041
are to be connected, the FS5 to FS12 signals have to be
generated externally. When using the framing signals
FS1 to FS4, no interface logic is required when using the
PCD5032 ADPCM CODEC.
A speech-slot control table is used to determine where to
store/fetch speech data for transmission and reception.
The hardware speech-interface is capable of addressing
the right speech buffer for the relevant speech slot, and will
maintain a counter carrying the offset to the correct
stored/fetched address.
6.4.2
M
UTING
Due to various reasons the quality of the incoming speech
data may be degraded significantly. By muting the speech
data, these disturbances are not audible (or are less
audible) to the user. The PCD5041 performs two types of
muting:
Fast muting
Slow muting.
Fast muting, which is performed by the PCD5041
automatically, is nothing more than a repetition of the
previously received frame (80 speech samples) to the
ADPCM CODEC. It is issued if no Sync word was
detected. Slow muting is issued by the microcontroller,
after having detected a degradation of quality. A slow mute
is implemented as a continuous ‘0000’ nibble transmission
to the ADPCM CODEC, until slow mute is released.
6.4.3
L
OCAL CALL
A local call option is implemented, in order to loopback
data from one CODEC to another CODEC, and vice versa,
see Fig.5.
handbook, halfpage
MBH710
0
1
speech slots
speech buffer
pair
0
1
DO
0
1
0
1
DI
Fig.5 Local call switching on speech interface.
6.5
RF interface
Most of the functions performed by the RF interface are
under control of the PCC. Specifically, the processing of
non-speech data and the programming of functions and
registers is done via the PCC.
6.5.1
S
ERIAL TRANSMITTER
The serial receiver processes the data, which comes from
the RF section, and which is already filtered by the
synchronization part. The data is latched, using the
recovered data clock.
The serial receiver will collect the complete A-field and
B-field and store it in the common data memory. Before the
A-field is received, the A-field start address is programmed
by the PCC. Upon reception of A-field nibbles, the address
is updated by the serial receiver. Meanwhile, the PCC will
program the B-field start address.
In Fig.6 the data flow in the serial receiver is shown. Note
that almost no decoding of messages is required. Only the
header of the A-field needs to be decoded to check if a
ciphered message is being received or transmitted, which
requires the ciphering to be switched on in the A-field also.
6.5.2
S
ERIAL RECEIVER
The serial transmitter performs the reverse of the receiver
functions. Several blocks used in the receiver are also
used in the transmitter. Amongst these are the
CRC-generators, the scrambler, and the address
registers. Figure 7 shows the serial transmitter structure.
By transmitting the X-CRC twice, the Z-field is transmitted.
The handling of the address registers is the same for the
transmitter. Transmission of the synchronization sequence
(S-field) is done using the same method as the A-field and
B-field. The S-field is stored in the common data memory
and will be fetched by the transmitter, just before
transmission.
Two additional functions are not shown in Fig.7:
In the handset the data in the serial transmitter may be
advanced by a programmable number of bit periods.
This is done to compensate for the delay in the RF
section
The transmitted data can be inverted (using a switch in
the PCD5041 mode register), in order to connect the
PCD5041 to VCOs requiring negative modulation.
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