1998 Jun 17
55
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
11 AC CHARACTERISTICS
T
amb
=
25 to +70
°
C, V
DD
= 1.8 to 3.6 V, f
EXTAL
= 76.8 kHz, maximum load capacitance = 50 pF connected to any
digital output; unless otherwise specified.
Notes
1.
T is one period of the 76.8 kHz clock source. Note that from power-up, the oscillator start-up time can influence the
availability and period of clock strobes. This can affect the RESET HIGH to READY LOW timing.
When the host re-programs an address word with a host-to-decoder packet ID > 7FH, there is an added delay before
the PCD5008 is ready for another packet.
2.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset timing
t
W(rst)
t
LH(RESET-READY)
t
HL(RESET-READY)
RESET pulse width
RESET LOW to READY HIGH
RESET HIGH to READY LOW stable 76.8 kHz clock
200
1
200
ns
ns
s
Start-up timing
t
strt(osc)
t
h(rst)
t
HL(RESET-READY)
t
WUL(osc-READY)
oscillator start-up time
RESET hold time
RESET HIGH to READY LOW note 1
oscillator warmed up to
READY LOW
see Fig.18
200
1
76800
1
s
ns
T
s
SPI timing
f
SCK
T
cy(SCK)
t
LEAD1
t
LAG1
t
d(SS-READY)
operating frequency
cycle time
select lead time
de-select lag time
SS-to-READY delay time
0
1000
200
200
1
80
MHz
ns
ns
ns
μ
s
previous packet did not program
an address word; note 2
previous packet programmed an
address word; note 2
420
μ
s
t
READYH
t
LEAD2
t
LAG2
t
su(i)(D)
t
h(i)(D)
t
ACC(o)
t
o(dis)
t
DOV
t
h(o)(D)
t
SSH
t
SCKH
t
SCKL
t
r
t
f
READY HIGH time
READY lead time
READY lag time
MOSI data setup time
MOSI data hold time
MISO access time
MISO disable time
MISO data valid time
MISO data hold time
SS HIGH time
SCK HIGH time
SCK LOW time
SCK rise time
SCK fall time
50
200
200
200
0
0
200
300
300
200
200
300
200
1
1
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
10% to 90% V
DD
10% to 90% V
DD