參數(shù)資料
型號: PCD5008
廠商: NXP Semiconductors N.V.
英文描述: FLEX Pager Decoder
中文描述: FleX創(chuàng)建傳呼機解碼器
文件頁數(shù): 18/64頁
文件大?。?/td> 341K
代理商: PCD5008
1998 Jun 17
18
Philips Semiconductors
Product specification
FLEX
Pager Decoder
PCD5008
Table 6
Input signal polarity
Table 7
FLEX
4 level FSK modulation selection
SP
1
SP
0
SIGNAL POLARITY
EXTS1
EXTS0
0
0
1
1
0
1
0
1
normal
normal
inverted
inverted
normal
inverted
normal
inverted
EXTS1
EXTS0
FSK MODULATION
AT SP = 0,0
(Hz)
1
1
0
0
0
1
1
0
+4800
+1600
1600
4800
8.4.5
P
ART
ID
PACKET
(ID = FFH)
The part ID packet is output by the PCD5008 SPI
whenever the SPI transmit is disabled due to the
checksum feature.
MDL:
model (Table 8). The PCD5008 model value is 0.
CID:
compatibility ID (Table 8). This value describes other
parts with the same model number, which are compatible
with this part. The PCD5008 compatibility value is 1.
Devices which implement a superset of PCD5008
functionality have MDL cleared and CID
0
set.
REV:
revision (Table 8). This identifies the manufacturing
version of the PCD5008. For the PCD5008 the value is 6.
Compatible parts have values in the range 0 to 5.
8.4.6
C
HECKSUM PACKET
(ID = 00H)
See Table 9 for checksum packet bit assignment.
CV
: checksum value (24 bits), see Section 8.4.2.
Table 8
Part ID packet bit assignments
Table 9
Checksum packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
1
1
1
1
1
1
1
1
MDL
1
CID
7
REV
7
MDL
0
CID
6
REV
6
CID
13
CID
5
REV
5
CID
12
CID
4
REV
4
CID
11
CID
3
REV
3
CID
10
CID
2
REV
2
CID
9
CID
1
REV
1
CID
8
CID
0
REV
0
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
0
0
CV
23
CV
15
CV
7
CV
22
CV
14
CV
6
CV
21
CV
13
CV
5
CV
20
CV
12
CV
4
CV
19
CV
11
CV
3
CV
18
CV
10
CV
2
CV
17
CV
9
CV
1
CV
16
CV
8
CV
0
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